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Fixed handling of boolean attributes (passes)

This commit is contained in:
Clifford Wolf 2013-10-24 11:37:54 +02:00
parent e9dede01ca
commit e679a5d046
6 changed files with 8 additions and 8 deletions
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2
kernel/rtlil.h
View File

@ -368,7 +368,7 @@ struct RTLIL::CaseRule {
struct RTLIL::SwitchRule { struct RTLIL::SwitchRule {
RTLIL::SigSpec signal; RTLIL::SigSpec signal;
std::map<RTLIL::IdString, RTLIL::Const> attributes; RTLIL_ATTRIBUTE_MEMBERS
std::vector<RTLIL::CaseRule*> cases; std::vector<RTLIL::CaseRule*> cases;
~SwitchRule(); ~SwitchRule();
void optimize(); void optimize();

4
passes/cmds/show.cc
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@ -477,7 +477,7 @@ struct ShowWorker
if (!design->selected_module(module->name)) if (!design->selected_module(module->name))
continue; continue;
if (design->selected_whole_module(module->name)) { if (design->selected_whole_module(module->name)) {
if (module->attributes.count("\\placeholder") > 0) { if (module->get_bool_attribute("\\placeholder") > 0) {
log("Skipping placeholder module %s.\n", id2cstr(module->name)); log("Skipping placeholder module %s.\n", id2cstr(module->name));
continue; continue;
} else } else
@ -617,7 +617,7 @@ struct ShowPass : public Pass {
if (format != "ps") { if (format != "ps") {
int modcount = 0; int modcount = 0;
for (auto &mod_it : design->modules) { for (auto &mod_it : design->modules) {
if (mod_it.second->attributes.count("\\placeholder") > 0) if (mod_it.second->get_bool_attribute("\\placeholder") > 0)
continue; continue;
if (mod_it.second->cells.empty() && mod_it.second->connections.empty()) if (mod_it.second->cells.empty() && mod_it.second->connections.empty())
continue; continue;

4
passes/hierarchy/hierarchy.cc
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@ -113,7 +113,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
RTLIL::Module *mod = new RTLIL::Module; RTLIL::Module *mod = new RTLIL::Module;
mod->name = celltype; mod->name = celltype;
mod->attributes["\\placeholder"] = RTLIL::Const(0, 0); mod->attributes["\\placeholder"] = RTLIL::Const(1);
design->modules[mod->name] = mod; design->modules[mod->name] = mod;
for (auto &decl : ports) { for (auto &decl : ports) {
@ -147,7 +147,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla
} }
if (cell->parameters.size() == 0) if (cell->parameters.size() == 0)
continue; continue;
if (design->modules.at(cell->type)->attributes.count("\\placeholder") > 0) if (design->modules.at(cell->type)->get_bool_attribute("\\placeholder"))
continue; continue;
RTLIL::Module *mod = design->modules[cell->type]; RTLIL::Module *mod = design->modules[cell->type];
cell->type = mod->derive(design, cell->parameters); cell->type = mod->derive(design, cell->parameters);

2
passes/opt/opt_clean.cc
View File

@ -47,7 +47,7 @@ static void rmunused_module_cells(RTLIL::Module *module, bool verbose)
wire2driver.insert(sig, cell); wire2driver.insert(sig, cell);
} }
} }
if (cell->type == "$memwr" || cell->attributes.count("\\keep")) if (cell->type == "$memwr" || cell->get_bool_attribute("\\keep"))
queue.insert(cell); queue.insert(cell);
unused.insert(cell); unused.insert(cell);
} }

2
passes/proc/proc_mux.cc
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@ -210,7 +210,7 @@ static RTLIL::SigSpec signal_to_mux_tree(RTLIL::Module *mod, RTLIL::CaseRule *cs
{ {
// detect groups of parallel cases // detect groups of parallel cases
std::vector<int> pgroups(sw->cases.size()); std::vector<int> pgroups(sw->cases.size());
if (sw->attributes.count("\\parallel_case") == 0) { if (!sw->get_bool_attribute("\\parallel_case")) {
BitPatternPool pool(sw->signal.width); BitPatternPool pool(sw->signal.width);
bool extra_group_for_next_case = false; bool extra_group_for_next_case = false;
for (size_t i = 0; i < sw->cases.size(); i++) { for (size_t i = 0; i < sw->cases.size(); i++) {

2
passes/techmap/iopadmap.cc
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@ -144,7 +144,7 @@ struct IopadmapPass : public Pass {
cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width); cell->parameters[RTLIL::escape_id(widthparam)] = RTLIL::Const(wire->width);
if (!nameparam.empty()) if (!nameparam.empty())
cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name)); cell->parameters[RTLIL::escape_id(nameparam)] = RTLIL::Const(RTLIL::id2cstr(wire->name));
cell->attributes["\\keep"] = RTLIL::Const(); cell->attributes["\\keep"] = RTLIL::Const(1);
module->add(cell); module->add(cell);
wire->port_id = 0; wire->port_id = 0;