mirror of https://github.com/YosysHQ/yosys.git
extract_reduce: Refactor and fix input signal construction.
Fixes #3047.
This commit is contained in:
Marcelina Kościelnicka
parent
a0e9d9fef9
commit
e64456f920
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@ -224,89 +224,60 @@ struct ExtractReducePass : public Pass
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if(consumed_cells.count(head_cell))
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if(consumed_cells.count(head_cell))
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continue;
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continue;
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pool<Cell*> cur_supercell;
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dict<SigBit, int> sources;
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int inner_cells = 0;
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std::deque<Cell*> bfs_queue = {head_cell};
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std::deque<Cell*> bfs_queue = {head_cell};
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while (bfs_queue.size())
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while (bfs_queue.size())
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{
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{
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Cell* x = bfs_queue.front();
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Cell* x = bfs_queue.front();
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bfs_queue.pop_front();
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bfs_queue.pop_front();
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cur_supercell.insert(x);
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for (auto port: {ID::A, ID::B}) {
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auto bit = sigmap(x->getPort(port)[0]);
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auto a = sigmap(x->getPort(ID::A));
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bool sink_single = sig_to_sink[bit].size() == 1 && !port_sigs.count(bit);
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log_assert(a.size() == 1);
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// Must have only one sink unless we're going off chain
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Cell* drv = sig_to_driver[bit];
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// XXX: Check that it is indeed this node?
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bool drv_ok = drv && drv->type == head_cell->type;
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if( allow_off_chain || (sig_to_sink[a[0]].size() + port_sigs.count(a[0]) == 1) )
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{
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Cell* cell_a = sig_to_driver[a[0]];
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if(cell_a && IsRightType(cell_a, gt))
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{
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// The cell here is the correct type, and it's definitely driving
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// this current cell.
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bfs_queue.push_back(cell_a);
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}
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}
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auto b = sigmap(x->getPort(ID::B));
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if (drv_ok && (allow_off_chain || sink_single)) {
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log_assert(b.size() == 1);
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inner_cells++;
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bfs_queue.push_back(drv);
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// Must have only one sink
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} else {
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// XXX: Check that it is indeed this node?
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sources[bit]++;
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if( allow_off_chain || (sig_to_sink[b[0]].size() + port_sigs.count(b[0]) == 1) )
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{
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Cell* cell_b = sig_to_driver[b[0]];
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if(cell_b && IsRightType(cell_b, gt))
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{
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// The cell here is the correct type, and it's definitely driving only
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// this current cell.
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bfs_queue.push_back(cell_b);
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}
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}
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}
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}
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}
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}
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log(" Cells:\n");
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if (inner_cells)
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for (auto x : cur_supercell)
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log(" %s\n", x->name.c_str());
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if (cur_supercell.size() > 1)
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{
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{
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// Worth it to create reduce cell
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// Worth it to create reduce cell
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log(" Creating $reduce_* cell!\n");
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log(" Creating $reduce_* cell!\n");
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pool<SigBit> input_pool;
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pool<SigBit> input_pool_intermed;
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for (auto x : cur_supercell)
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{
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input_pool.insert(sigmap(x->getPort(ID::A))[0]);
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input_pool.insert(sigmap(x->getPort(ID::B))[0]);
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input_pool_intermed.insert(sigmap(x->getPort(ID::Y))[0]);
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}
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SigSpec input;
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for (auto b : input_pool)
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if (input_pool_intermed.count(b) == 0)
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input.append(b);
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SigBit output = sigmap(head_cell->getPort(ID::Y)[0]);
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SigBit output = sigmap(head_cell->getPort(ID::Y)[0]);
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auto new_reduce_cell = module->addCell(NEW_ID,
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SigSpec input;
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gt == GateType::And ? ID($reduce_and) :
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for (auto it : sources) {
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gt == GateType::Or ? ID($reduce_or) :
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bool cond;
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gt == GateType::Xor ? ID($reduce_xor) : "");
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if (head_cell->type == ID($_XOR_))
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new_reduce_cell->setParam(ID::A_SIGNED, 0);
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cond = it.second & 1;
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new_reduce_cell->setParam(ID::A_WIDTH, input.size());
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else
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new_reduce_cell->setParam(ID::Y_WIDTH, 1);
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cond = it.second != 0;
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new_reduce_cell->setPort(ID::A, input);
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if (cond)
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new_reduce_cell->setPort(ID::Y, output);
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input.append(it.first);
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if(allow_off_chain)
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consumed_cells.insert(head_cell);
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else
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{
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for (auto x : cur_supercell)
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consumed_cells.insert(x);
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}
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}
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if (head_cell->type == ID($_AND_)) {
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module->addReduceAnd(NEW_ID, input, output);
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} else if (head_cell->type == ID($_OR_)) {
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module->addReduceOr(NEW_ID, input, output);
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} else if (head_cell->type == ID($_XOR_)) {
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module->addReduceXor(NEW_ID, input, output);
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} else {
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log_assert(false);
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}
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consumed_cells.insert(head_cell);
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}
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}
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}
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}
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}
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}
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@ -0,0 +1,12 @@
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read_verilog << EOT
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module test (A, B, C, D, Y);
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input A, B, C, D;
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output Y;
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assign Y = A^B^C^D^A;
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endmodule
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EOT
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techmap
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equiv_opt -assert extract_reduce
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