mirror of https://github.com/YosysHQ/yosys.git
Parallel wallace tree
Signed-off-by: andyfox-rushc <andy@rushc.com>
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@ -380,11 +380,8 @@ struct BoothPassWorker {
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#ifdef DEBUG_CSA
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DebugDumpAlignPP(aligned_pp);
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#endif
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// SigSig wtree_sum = WallaceSum(z_sz, aligned_pp);
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SigSpec s_vec;
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SigSpec c_vec;
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std::vector<std::vector<RTLIL::Cell *>> debug_csa_trees;
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BuildCSATree(module, aligned_pp, s_vec, c_vec, debug_csa_trees);
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#ifdef DEBUG_CSA
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@ -393,6 +390,7 @@ struct BoothPassWorker {
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printf("Carry Vec %s \n", c_vec.as_string().c_str());
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printf("Size of Sum %d Size of Result %d\n", s_vec.size(), Z.size());
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#endif
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// Debug code: Dump out the csa trees
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// DumpCSATrees(debug_csa_trees);
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// BuildCPA(module, s_vec, c_vec, Z);
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@ -411,8 +409,9 @@ struct BoothPassWorker {
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SigSpec g = module->addWire(NEW_ID, s_vec.size());
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SigSpec p = module->addWire(NEW_ID, s_vec.size());
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SigSpec co = module->addWire(NEW_ID, s_vec.size());
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module->addAnd(NEW_ID, s_vec, {c_vec.extract(0, c_vec.size() - 1), State::S0}, g);
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module->addXor(NEW_ID, s_vec, {c_vec.extract(0, c_vec.size() - 1), State::S0}, p);
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module->addAnd(NEW_ID, s_vec, {c_vec.extract(0, c_vec.size() - 1), State::S0}, g); // generate
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module->addXor(NEW_ID, s_vec, {c_vec.extract(0, c_vec.size() - 1), State::S0}, p); // propagate
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auto lcu = module->addCell(NEW_ID, ID($lcu));
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auto lcu_int = module->addWire(NEW_ID, s_vec.size());
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lcu->setParam(ID::WIDTH, s_vec.size());
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@ -746,7 +745,6 @@ struct BoothPassWorker {
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SigSpec &carry_bits_to_sum, std::vector<std::vector<RTLIL::Cell *>> &debug_csa_trees)
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{
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(void)column_ix;
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#ifdef DEBUG_CSA
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if (column_bits.size() > 0)
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printf("Parallel Column %d reduce bits parallel given %d bits (%s) to reduce\n", column_ix, column_bits.size(),
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@ -842,10 +840,9 @@ struct BoothPassWorker {
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}
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printf("\n");
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#endif
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// Build parallel reduction tree
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SigBit s, c;
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ReduceBitsParallel(module, column_ix, column_bits, s, c, carry_bits_to_add_to_next_column, debug_csa_trees);
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s_vec.append(s);
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c_vec.append(c);
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@ -1020,7 +1017,7 @@ struct BoothPassWorker {
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// Sum the bits in the current column
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// Pass the carry bits from each csa to the next
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// column for summation.
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// column for summation. Build serial tree
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void ReduceBits(RTLIL::Module *module, int column_ix, SigSpec column_bits, SigBit &s_result, SigBit &c_result, SigSpec &carry_bits_to_sum,
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std::vector<std::vector<RTLIL::Cell *>> &debug_csa_trees)
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@ -1396,8 +1393,7 @@ struct BoothPass : public Pass {
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}
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void execute(vector<string> args, RTLIL::Design *design) override
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{
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log_header(design, "Executing BOOTH pass (map to Booth multipliers).\n");
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log_header(design, "**Executing BOOTH pass (map to Booth multipliers).\n");
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size_t argidx;
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bool mapped_cpa = false;
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bool lowpower = false;
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@ -1424,8 +1420,7 @@ struct BoothPass : public Pass {
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total += worker.booth_counter;
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}
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}
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log("Mapped %d multipliers.\n", total);
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log_header(design, "Mapped %d multipliers.\n", total);
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}
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} MultPass;
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