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Fixed data width

This commit is contained in:
Miodrag Milanovic 2019-08-11 10:46:48 +02:00
parent 8c8100e0df
commit e609537e38
1 changed files with 2 additions and 2 deletions
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4
techlibs/efinix/brams_map.v
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@ -22,8 +22,8 @@ module \$__EFINIX_5K (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN);
localparam WRITEMODE_A = TRANSP2 ? "WRITE_FIRST" : "READ_FIRST";
EFX_RAM_5K #(
.READ_WIDTH(20),
.WRITE_WIDTH(20),
.READ_WIDTH(CFG_DBITS),
.WRITE_WIDTH(CFG_DBITS),
.OUTPUT_REG(1'b0),
.RCLK_POLARITY(1'b1),
.RE_POLARITY(1'b1),