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Merge pull request #4057 from jix/peepopt_shiftmul_right_padding_fix 

peepopt: Fix padding for the peepopt_shiftmul_right pattern
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Martin Povišer 2023-12-07 14:56:53 +01:00 committed by GitHub
parent fb4cbfa735 7b74caa5db
commit e6021b2b48
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2 changed files with 32 additions and 13 deletions
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19
passes/pmgen/peepopt_shiftmul_right.pmg
View File

@ -82,22 +82,17 @@ code
int new_const_factor = 1 << factor_bits; int new_const_factor = 1 << factor_bits;
SigSpec padding(State::Sx, new_const_factor-const_factor); SigSpec padding(State::Sx, new_const_factor-const_factor);
SigSpec old_a = port(shift, \A), new_a; SigSpec old_a = port(shift, \A), new_a;
int trunc = 0;
if (GetSize(old_a) % const_factor != 0) {
trunc = const_factor - GetSize(old_a) % const_factor;
old_a.append(SigSpec(State::Sx, trunc));
}
for (int i = 0; i*const_factor < GetSize(old_a); i++) { for (int i = 0; i*const_factor < GetSize(old_a); i++) {
SigSpec slice = old_a.extract(i*const_factor, const_factor); if ((i+1)*const_factor < GetSize(old_a)) {
new_a.append(slice); SigSpec slice = old_a.extract(i*const_factor, const_factor);
new_a.append(padding); new_a.append(slice);
new_a.append(padding);
} else {
new_a.append(old_a.extract_end(i*const_factor));
}
} }
if (trunc > 0)
new_a.remove(GetSize(new_a)-trunc, trunc);
SigSpec new_b = {mul_din, SigSpec(State::S0, factor_bits)}; SigSpec new_b = {mul_din, SigSpec(State::S0, factor_bits)};
if (param(shift, \B_SIGNED).as_bool()) if (param(shift, \B_SIGNED).as_bool())
new_b.append(State::S0); new_b.append(State::S0);

26
tests/various/peepopt.ys
View File

@ -46,7 +46,31 @@ design -import gold -as gold peepopt_shiftmul_2
design -import gate -as gate peepopt_shiftmul_2 design -import gate -as gate peepopt_shiftmul_2
miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter
sat -show-public -enable_undef -prove-asserts miter sat -verify -show-public -enable_undef -prove-asserts miter
cd gate
select -assert-count 1 t:$shr
select -assert-count 1 t:$mul
select -assert-count 0 t:$shr t:$mul %% t:* %D
####################
design -reset
read_verilog <<EOT
module peepopt_shiftmul_3 (input [7:0] D, input [0:0] S, output [3:0] Y);
assign Y = D >> (S*5);
endmodule
EOT
prep
design -save gold
peepopt
design -stash gate
design -import gold -as gold peepopt_shiftmul_3
design -import gate -as gate peepopt_shiftmul_3
miter -equiv -make_assert -make_outputs -ignore_gold_x -flatten gold gate miter
sat -verify -show-public -enable_undef -prove-asserts miter
cd gate cd gate
select -assert-count 1 t:$shr select -assert-count 1 t:$shr
select -assert-count 1 t:$mul select -assert-count 1 t:$mul