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Fix input vector for reduce cells. Infinite loop fixed.

This commit is contained in:
Kaj Tuomi 2017-10-17 09:58:01 +03:00
parent 778df553ed
commit e558b3284b
1 changed files with 2 additions and 0 deletions
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2
passes/opt/opt_reduce.cc
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@ -44,6 +44,7 @@ struct OptReduceWorker
cells.erase(cell); cells.erase(cell);
RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A")); RTLIL::SigSpec sig_a = assign_map(cell->getPort("\\A"));
sig_a.sort_and_unify();
pool<RTLIL::SigBit> new_sig_a_bits; pool<RTLIL::SigBit> new_sig_a_bits;
for (auto &bit : sig_a.to_sigbit_set()) for (auto &bit : sig_a.to_sigbit_set())
@ -86,6 +87,7 @@ struct OptReduceWorker
} }
RTLIL::SigSpec new_sig_a(new_sig_a_bits); RTLIL::SigSpec new_sig_a(new_sig_a_bits);
new_sig_a.sort_and_unify();
if (new_sig_a != sig_a || sig_a.size() != cell->getPort("\\A").size()) { if (new_sig_a != sig_a || sig_a.size() != cell->getPort("\\A").size()) {
log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a)); log(" New input vector for %s cell %s: %s\n", cell->type.c_str(), cell->name.c_str(), log_signal(new_sig_a));