mirror of https://github.com/YosysHQ/yosys.git
Add "yosys-smtbmc --aig-noheader" and AIGER mem init support
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45e10c1c89
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@ -30,6 +30,7 @@ append_steps = 0
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vcdfile = None
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cexfile = None
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aigprefix = None
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aigheader = True
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vlogtbfile = None
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inconstr = list()
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outconstr = None
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@ -73,6 +74,10 @@ yosys-smtbmc [options] <yosys_smt2_output>
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and AIGER witness file. The file names are <prefix>.aim for
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the map file and <prefix>.aiw for the witness file.
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--aig-noheader
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the AIGER witness file does not include the status and
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properties lines.
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--noinfo
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only run the core proof, do not collect and print any
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additional information (e.g. which assert failed)
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@ -111,7 +116,7 @@ yosys-smtbmc [options] <yosys_smt2_output>
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try:
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opts, args = getopt.getopt(sys.argv[1:], so.shortopts + "t:igm:", so.longopts +
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["final-only", "assume-skipped=", "smtc=", "cex=", "aig=",
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["final-only", "assume-skipped=", "smtc=", "cex=", "aig=", "aig-noheader",
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"dump-vcd=", "dump-vlogtb=", "dump-smtc=", "dump-all", "noinfo", "append="])
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except:
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usage()
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@ -141,6 +146,8 @@ for o, a in opts:
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cexfile = a
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elif o == "--aig":
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aigprefix = a
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elif o == "--aig-noheader":
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aigheader = False
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elif o == "--dump-vcd":
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vcdfile = a
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elif o == "--dump-vlogtb":
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@ -411,6 +418,9 @@ if aigprefix is not None:
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got_ffinit = False
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step = 0
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if not aigheader:
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got_state = True
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for entry in f.read().splitlines():
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if len(entry) == 0 or entry[0] in "bcjfu.":
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continue
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@ -458,13 +468,30 @@ if aigprefix is not None:
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bitidx = init_map[i][1]
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path = smt.get_path(topmod, name)
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width = smt.net_width(topmod, path)
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if not smt.net_exists(topmod, path):
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match = re.match(r"(.*)\[(\d+)\]$", path[-1])
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if match:
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path[-1] = match.group(1)
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addr = int(match.group(2))
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if not match or not smt.mem_exists(topmod, path):
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print_msg("Ignoring init value for unknown net: %s" % (name))
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continue
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meminfo = smt.mem_info(topmod, path)
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smtexpr = "(select [%s] #b%s)" % (".".join(path), bin(addr)[2:].zfill(meminfo[0]))
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width = meminfo[1]
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else:
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smtexpr = "[%s]" % name
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width = smt.net_width(topmod, path)
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if width == 1:
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assert bitidx == 0
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smtexpr = "(= [%s] %s)" % (name, "true" if value else "false")
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smtexpr = "(= %s %s)" % (smtexpr, "true" if value else "false")
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else:
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smtexpr = "(= ((_ extract %d %d) [%s]) #b%d)" % (bitidx, bitidx, name, value)
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smtexpr = "(= ((_ extract %d %d) %s) #b%d)" % (bitidx, bitidx, smtexpr, value)
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constr_assumes[0].append((cexfile, smtexpr))
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@ -569,7 +596,7 @@ def write_vlogtb_trace(steps_start, steps_stop, index):
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mems = sorted(smt.hiermems(topmod))
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for mempath in mems:
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abits, width, ports = smt.mem_info(topmod, "s%d" % steps_start, mempath)
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abits, width, ports = smt.mem_info(topmod, mempath)
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mem = smt.mem_expr(topmod, "s%d" % steps_start, mempath)
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addr_expr_list = list()
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@ -630,7 +657,7 @@ def write_constr_trace(steps_start, steps_stop, index):
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mems = sorted(smt.hiermems(topmod))
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for mempath in mems:
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abits, width, ports = smt.mem_info(topmod, "s%d" % steps_start, mempath)
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abits, width, ports = smt.mem_info(topmod, mempath)
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mem = smt.mem_expr(topmod, "s%d" % steps_start, mempath)
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addr_expr_list = list()
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@ -567,6 +567,26 @@ class SmtIo:
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assert net_path[-1] in self.modinfo[mod].wsize
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return self.modinfo[mod].wsize[net_path[-1]]
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def net_exists(self, mod, net_path):
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for i in range(len(net_path)-1):
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if mod not in self.modinfo: return False
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if net_path[i] not in self.modinfo[mod].cells: return False
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mod = self.modinfo[mod].cells[net_path[i]]
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if mod not in self.modinfo: return False
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if net_path[-1] not in self.modinfo[mod].wsize: return False
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return True
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def mem_exists(self, mod, mem_path):
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for i in range(len(mem_path)-1):
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if mod not in self.modinfo: return False
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if mem_path[i] not in self.modinfo[mod].cells: return False
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mod = self.modinfo[mod].cells[mem_path[i]]
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if mod not in self.modinfo: return False
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if mem_path[-1] not in self.modinfo[mod].memories: return False
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return True
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def mem_expr(self, mod, base, path, portidx=None, infomode=False):
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if len(path) == 1:
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assert mod in self.modinfo
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@ -582,8 +602,8 @@ class SmtIo:
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nextbase = "(|%s_h %s| %s)" % (mod, path[0], base)
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return self.mem_expr(nextmod, nextbase, path[1:], portidx=portidx, infomode=infomode)
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def mem_info(self, mod, base, path):
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return self.mem_expr(mod, base, path, infomode=True)
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def mem_info(self, mod, path):
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return self.mem_expr(mod, "", path, infomode=True)
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def get_net(self, mod_name, net_path, state_name):
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return self.get(self.net_expr(mod_name, state_name, net_path))
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