mirror of https://github.com/YosysHQ/yosys.git
MultPassWorker -> BoothPassWorker
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parent
eccc0ae6db
commit
e4fe522767
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@ -58,13 +58,13 @@ synth -top my_design -booth
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USING_YOSYS_NAMESPACE
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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PRIVATE_NAMESPACE_BEGIN
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struct MultPassWorker {
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struct BoothPassWorker {
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RTLIL::Module *module;
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RTLIL::Module *module;
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SigMap sigmap;
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SigMap sigmap;
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int booth_counter;
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int booth_counter;
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MultPassWorker(RTLIL::Module *module) : module(module), sigmap(module) { booth_counter = 0; }
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BoothPassWorker(RTLIL::Module *module) : module(module), sigmap(module) { booth_counter = 0; }
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// Helper routines for building architecture subcomponents
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// Helper routines for building architecture subcomponents
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@ -1505,15 +1505,16 @@ struct MultPassWorker {
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}
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}
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};
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};
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struct MultPass : public Pass {
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struct BoothPass : public Pass {
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MultPass() : Pass("booth", "Map $mul to booth multipliers") {}
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BoothPass() : Pass("booth", "Map $mul to booth multipliers") {}
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void execute(vector<string> args, RTLIL::Design *design) override
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void execute(vector<string> args, RTLIL::Design *design) override
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{
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{
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(void)args;
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(void)args;
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log_header(design, "Executing multpass. Generating Booth Multiplier structures for signed/unsigned multipliers of 4 bits or more\n");
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log_header(design,
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"Executing booth pass. Generating Booth Multiplier structures for signed/unsigned multipliers of 4 bits or more\n");
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for (auto mod : design->selected_modules())
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for (auto mod : design->selected_modules())
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if (!mod->has_processes_warn()) {
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if (!mod->has_processes_warn()) {
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MultPassWorker worker(mod);
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BoothPassWorker worker(mod);
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worker.run();
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worker.run();
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log_header(design, "Created %d booth multipliers.\n", worker.booth_counter);
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log_header(design, "Created %d booth multipliers.\n", worker.booth_counter);
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}
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}
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