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gowin: Use `memory_libmap` pass.

This commit is contained in:
Marcelina Kościelnicka 2022-02-09 09:25:45 +01:00
parent 0a8eaca322
commit e4d811561c
9 changed files with 565 additions and 255 deletions
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2
techlibs/gowin/.gitignore vendored
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@ -1,2 +0,0 @@
brams_init.mk
bram_init_*.vh

15
techlibs/gowin/Makefile.inc
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@ -1,8 +1,6 @@
OBJS += techlibs/gowin/synth_gowin.o OBJS += techlibs/gowin/synth_gowin.o
GENFILES += techlibs/gowin/bram_init_16.vh
$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_map.v)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_map.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_sim.v)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/cells_sim.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/arith_map.v)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/arith_map.v))
@ -10,16 +8,3 @@ $(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_map.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams.txt)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/brams.txt))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams_map.v)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams_map.v))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams.txt)) $(eval $(call add_share_file,share/gowin,techlibs/gowin/lutrams.txt))
$(eval $(call add_share_file,share/gowin,techlibs/gowin/brams_init3.vh))
EXTRA_OBJS += techlibs/gowin/brams_init.mk
.SECONDARY: techlibs/gowin/brams_init.mk
techlibs/gowin/brams_init.mk: techlibs/gowin/brams_init.py
$(Q) mkdir -p techlibs/gowin
$(P) python3 $<
$(Q) touch $@
techlibs/gowin/bram_init_16.vh: techlibs/gowin/brams_init.mk
$(eval $(call add_gen_share_file,share/gowin,techlibs/gowin/bram_init_16.vh))

110
techlibs/gowin/brams.txt
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@ -1,31 +1,81 @@
bram $__GW1NR_SDP ram block $__GOWIN_SP_ {
init 1 abits 14;
abits 9 @a9d36 widths 1 2 4 9 18 36 per_port;
dbits 32 @a9d36 byte 9;
abits 10 @a10d18 cost 128;
dbits 16 @a10d18 init no_undef;
abits 11 @a11d9 port srsw "A" {
dbits 8 @a11d9 clock posedge;
abits 12 @a12d4 clken;
dbits 4 @a12d4 wrbe_separate;
abits 13 @a13d2 option "RESET_MODE" "SYNC" {
dbits 2 @a13d2 rdsrst zero ungated;
abits 14 @a14d1 }
dbits 1 @a14d1 option "RESET_MODE" "ASYNC" {
groups 2 rdarst zero;
ports 1 1 }
wrmode 1 0 rdinit zero;
enable 4 1 @a9d36 portoption "WRITE_MODE" 0 {
enable 2 1 @a10d18 rdwr no_change;
enable 1 1 @a11d9 @a12d4 @a13d2 @a14d1 }
transp 0 0 portoption "WRITE_MODE" 1 {
clocks 2 3 rdwr new;
clkpol 2 3 }
endbram portoption "WRITE_MODE" 2 {
rdwr old;
}
}
}
match $__GW1NR_SDP ram block $__GOWIN_DP_ {
min bits 2048 abits 14;
min efficiency 5 widths 1 2 4 9 18 per_port;
shuffle_enable A byte 9;
make_transp cost 128;
endmatch init no_undef;
port srsw "A" "B" {
clock posedge;
clken;
wrbe_separate;
option "RESET_MODE" "SYNC" {
rdsrst zero ungated;
}
option "RESET_MODE" "ASYNC" {
rdarst zero;
}
rdinit zero;
portoption "WRITE_MODE" 0 {
rdwr no_change;
}
portoption "WRITE_MODE" 1 {
rdwr new;
}
portoption "WRITE_MODE" 2 {
rdwr old;
}
}
}
ram block $__GOWIN_SDP_ {
abits 14;
widths 1 2 4 9 18 36 per_port;
byte 9;
cost 128;
init no_undef;
port sr "R" {
clock posedge;
clken;
option "RESET_MODE" "SYNC" {
rdsrst zero ungated;
}
option "RESET_MODE" "ASYNC" {
rdarst zero;
}
rdinit zero;
}
port sw "W" {
clock posedge;
clken;
wrbe_separate;
}
}

8
techlibs/gowin/brams_init.py
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@ -1,8 +0,0 @@
#!/usr/bin/env python3
with open("techlibs/gowin/bram_init_16.vh", "w") as f:
for i in range(0, 0x40):
low = i << 8
hi = ((i+1) << 8)-1
snippet = "INIT[%d:%d]" % (hi, low)
print(".INIT_RAM_%02X({%s})," % (i, snippet), file=f)

12
techlibs/gowin/brams_init3.vh
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@ -1,12 +0,0 @@
localparam [15:0] INIT_0 = {
INIT[ 60], INIT[ 56], INIT[ 52], INIT[ 48], INIT[ 44], INIT[ 40], INIT[ 36], INIT[ 32], INIT[ 28], INIT[ 24], INIT[ 20], INIT[ 16], INIT[ 12], INIT[ 8], INIT[ 4], INIT[ 0]
};
localparam [15:0] INIT_1 = {
INIT[ 61], INIT[ 57], INIT[ 53], INIT[ 49], INIT[ 45], INIT[ 41], INIT[ 37], INIT[ 33], INIT[ 29], INIT[ 25], INIT[ 21], INIT[ 17], INIT[ 13], INIT[ 9], INIT[ 5], INIT[ 1]
};
localparam [15:0] INIT_2 = {
INIT[ 62], INIT[ 58], INIT[ 54], INIT[ 50], INIT[ 46], INIT[ 42], INIT[ 38], INIT[ 34], INIT[ 30], INIT[ 26], INIT[ 22], INIT[ 18], INIT[ 14], INIT[ 10], INIT[ 6], INIT[ 2]
};
localparam [15:0] INIT_3 = {
INIT[ 63], INIT[ 59], INIT[ 55], INIT[ 51], INIT[ 47], INIT[ 43], INIT[ 39], INIT[ 35], INIT[ 31], INIT[ 27], INIT[ 23], INIT[ 19], INIT[ 15], INIT[ 11], INIT[ 7], INIT[ 3]
};

540
techlibs/gowin/brams_map.v
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@ -1,142 +1,410 @@
/* Semi Dual Port (SDP) memory have the following configurations: `define DEF_FUNCS \
* Memory Config RAM(BIT) Port Mode Memory Depth Data Depth function [255:0] init_slice_x8; \
* ----------------|---------| ----------|--------------|------------| input integer idx; \
* B-SRAM_16K_SD1 16K 16Kx1 16,384 1 integer i; \
* B-SRAM_8K_SD2 16K 8Kx2 8,192 2 for (i = 0; i < 32; i = i + 1) begin \
* B-SRAM_4K_SD4 16K 4Kx2 4,096 4 init_slice_x8[i*8+:8] = INIT[(idx * 32 + i) * 9+:8]; \
*/ end \
module \$__GW1NR_SDP (CLK2, CLK3, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); endfunction \
parameter CFG_ABITS = 10; function [287:0] init_slice_x9; \
parameter CFG_DBITS = 16; input integer idx; \
parameter CFG_ENABLE_A = 1; init_slice_x9 = INIT[idx * 288+:288]; \
parameter [16383:0] INIT = 16384'hx; endfunction \
parameter CLKPOL2 = 1;
parameter CLKPOL3 = 1;
input CLK2; `define x8_width(width) (width / 9 * 8 + width % 9)
input CLK3; `define x8_rd_data(data) {1'bx, data[31:24], 1'bx, data[23:16], 1'bx, data[15:8], 1'bx, data[7:0]}
`define x8_wr_data(data) {data[34:27], data[25:18], data[16:9], data[7:0]}
`define wre(width, wr_en, wr_be) (width < 18 ? wr_en | wr_be[0] : wr_en)
`define addrbe(width, addr, wr_be) (width < 18 ? addr : {addr[13:4], wr_be})
input [CFG_ABITS-1:0] A1ADDR;
input [CFG_DBITS-1:0] A1DATA;
input [CFG_ENABLE_A-1:0] A1EN;
input [CFG_ABITS-1:0] B1ADDR; `define INIT(func) \
output [CFG_DBITS-1:0] B1DATA; .INIT_RAM_00(func('h00)), \
input B1EN; .INIT_RAM_01(func('h01)), \
.INIT_RAM_02(func('h02)), \
.INIT_RAM_03(func('h03)), \
.INIT_RAM_04(func('h04)), \
.INIT_RAM_05(func('h05)), \
.INIT_RAM_06(func('h06)), \
.INIT_RAM_07(func('h07)), \
.INIT_RAM_08(func('h08)), \
.INIT_RAM_09(func('h09)), \
.INIT_RAM_0A(func('h0a)), \
.INIT_RAM_0B(func('h0b)), \
.INIT_RAM_0C(func('h0c)), \
.INIT_RAM_0D(func('h0d)), \
.INIT_RAM_0E(func('h0e)), \
.INIT_RAM_0F(func('h0f)), \
.INIT_RAM_10(func('h10)), \
.INIT_RAM_11(func('h11)), \
.INIT_RAM_12(func('h12)), \
.INIT_RAM_13(func('h13)), \
.INIT_RAM_14(func('h14)), \
.INIT_RAM_15(func('h15)), \
.INIT_RAM_16(func('h16)), \
.INIT_RAM_17(func('h17)), \
.INIT_RAM_18(func('h18)), \
.INIT_RAM_19(func('h19)), \
.INIT_RAM_1A(func('h1a)), \
.INIT_RAM_1B(func('h1b)), \
.INIT_RAM_1C(func('h1c)), \
.INIT_RAM_1D(func('h1d)), \
.INIT_RAM_1E(func('h1e)), \
.INIT_RAM_1F(func('h1f)), \
.INIT_RAM_20(func('h20)), \
.INIT_RAM_21(func('h21)), \
.INIT_RAM_22(func('h22)), \
.INIT_RAM_23(func('h23)), \
.INIT_RAM_24(func('h24)), \
.INIT_RAM_25(func('h25)), \
.INIT_RAM_26(func('h26)), \
.INIT_RAM_27(func('h27)), \
.INIT_RAM_28(func('h28)), \
.INIT_RAM_29(func('h29)), \
.INIT_RAM_2A(func('h2a)), \
.INIT_RAM_2B(func('h2b)), \
.INIT_RAM_2C(func('h2c)), \
.INIT_RAM_2D(func('h2d)), \
.INIT_RAM_2E(func('h2e)), \
.INIT_RAM_2F(func('h2f)), \
.INIT_RAM_30(func('h30)), \
.INIT_RAM_31(func('h31)), \
.INIT_RAM_32(func('h32)), \
.INIT_RAM_33(func('h33)), \
.INIT_RAM_34(func('h34)), \
.INIT_RAM_35(func('h35)), \
.INIT_RAM_36(func('h36)), \
.INIT_RAM_37(func('h37)), \
.INIT_RAM_38(func('h38)), \
.INIT_RAM_39(func('h39)), \
.INIT_RAM_3A(func('h3a)), \
.INIT_RAM_3B(func('h3b)), \
.INIT_RAM_3C(func('h3c)), \
.INIT_RAM_3D(func('h3d)), \
.INIT_RAM_3E(func('h3e)), \
.INIT_RAM_3F(func('h3f)),
wire [31-CFG_DBITS:0] open; module $__GOWIN_SP_ (...);
parameter INIT = 0;
parameter OPTION_RESET_MODE = "SYNC";
parameter PORT_A_WIDTH = 36;
parameter PORT_A_WR_BE_WIDTH = 4;
parameter PORT_A_OPTION_WRITE_MODE = 0;
input PORT_A_CLK;
input PORT_A_CLK_EN;
input PORT_A_WR_EN;
input PORT_A_RD_SRST;
input PORT_A_RD_ARST;
input [13:0] PORT_A_ADDR;
input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;
input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
`DEF_FUNCS
wire RST = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST;
wire WRE = `wre(PORT_A_WIDTH, PORT_A_WR_EN, PORT_A_WR_BE);
wire [13:0] AD = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_A_WR_BE);
generate
if (PORT_A_WIDTH < 9) begin
wire [31:0] DI = `x8_wr_data(PORT_A_WR_DATA);
wire [31:0] DO;
assign PORT_A_RD_DATA = `x8_rd_data(DO);
SP #(
`INIT(init_slice_x8)
.READ_MODE(1'b0),
.WRITE_MODE(PORT_A_OPTION_WRITE_MODE),
.BIT_WIDTH(`x8_width(PORT_A_WIDTH)),
.BLK_SEL(3'b000),
.RESET_MODE(OPTION_RESET_MODE),
) _TECHMAP_REPLACE_ (
.BLKSEL(3'b000),
.CLK(PORT_A_CLK),
.CE(PORT_A_CLK_EN),
.WRE(WRE),
.RESET(RST),
.OCE(1'b0),
.AD(AD),
.DI(DI),
.DO(DO),
);
end else begin
wire [35:0] DI = PORT_A_WR_DATA;
wire [35:0] DO;
assign PORT_A_RD_DATA = DO;
SPX9 #(
`INIT(init_slice_x9)
.READ_MODE(1'b0),
.WRITE_MODE(PORT_A_OPTION_WRITE_MODE),
.BIT_WIDTH(PORT_A_WIDTH),
.BLK_SEL(3'b000),
.RESET_MODE(OPTION_RESET_MODE),
) _TECHMAP_REPLACE_ (
.BLKSEL(3'b000),
.CLK(PORT_A_CLK),
.CE(PORT_A_CLK_EN),
.WRE(WRE),
.RESET(RST),
.OCE(1'b0),
.AD(AD),
.DI(DI),
.DO(DO),
);
end
endgenerate
endmodule
module $__GOWIN_DP_ (...);
parameter INIT = 0;
parameter OPTION_RESET_MODE = "SYNC";
parameter PORT_A_WIDTH = 18;
parameter PORT_A_WR_BE_WIDTH = 2;
parameter PORT_A_OPTION_WRITE_MODE = 0;
parameter PORT_B_WIDTH = 18;
parameter PORT_B_WR_BE_WIDTH = 2;
parameter PORT_B_OPTION_WRITE_MODE = 0;
input PORT_A_CLK;
input PORT_A_CLK_EN;
input PORT_A_WR_EN;
input PORT_A_RD_SRST;
input PORT_A_RD_ARST;
input [13:0] PORT_A_ADDR;
input [PORT_A_WR_BE_WIDTH-1:0] PORT_A_WR_BE;
input [PORT_A_WIDTH-1:0] PORT_A_WR_DATA;
output [PORT_A_WIDTH-1:0] PORT_A_RD_DATA;
input PORT_B_CLK;
input PORT_B_CLK_EN;
input PORT_B_WR_EN;
input PORT_B_RD_SRST;
input PORT_B_RD_ARST;
input [13:0] PORT_B_ADDR;
input [PORT_A_WR_BE_WIDTH-1:0] PORT_B_WR_BE;
input [PORT_A_WIDTH-1:0] PORT_B_WR_DATA;
output [PORT_A_WIDTH-1:0] PORT_B_RD_DATA;
`DEF_FUNCS
wire RSTA = OPTION_RESET_MODE == "SYNC" ? PORT_A_RD_SRST : PORT_A_RD_ARST;
wire RSTB = OPTION_RESET_MODE == "SYNC" ? PORT_B_RD_SRST : PORT_B_RD_ARST;
wire WREA = `wre(PORT_A_WIDTH, PORT_A_WR_EN, PORT_A_WR_BE);
wire WREB = `wre(PORT_B_WIDTH, PORT_B_WR_EN, PORT_B_WR_BE);
wire [13:0] ADA = `addrbe(PORT_A_WIDTH, PORT_A_ADDR, PORT_A_WR_BE);
wire [13:0] ADB = `addrbe(PORT_B_WIDTH, PORT_B_ADDR, PORT_B_WR_BE);
generate
if (PORT_A_WIDTH < 9 || PORT_B_WIDTH < 9) begin
wire [15:0] DIA = `x8_wr_data(PORT_A_WR_DATA);
wire [15:0] DIB = `x8_wr_data(PORT_B_WR_DATA);
wire [15:0] DOA;
wire [15:0] DOB;
assign PORT_A_RD_DATA = `x8_rd_data(DOA);
assign PORT_B_RD_DATA = `x8_rd_data(DOB);
DP #(
`INIT(init_slice_x8)
.READ_MODE0(1'b0),
.READ_MODE1(1'b0),
.WRITE_MODE0(PORT_A_OPTION_WRITE_MODE),
.WRITE_MODE1(PORT_B_OPTION_WRITE_MODE),
.BIT_WIDTH_0(`x8_width(PORT_A_WIDTH)),
.BIT_WIDTH_1(`x8_width(PORT_B_WIDTH)),
.BLK_SEL(3'b000),
.RESET_MODE(OPTION_RESET_MODE),
) _TECHMAP_REPLACE_ (
.BLKSEL(3'b000),
.CLKA(PORT_A_CLK),
.CEA(PORT_A_CLK_EN),
.WREA(WREA),
.RESETA(RSTA),
.OCEA(1'b0),
.ADA(ADA),
.DIA(DIA),
.DOA(DOA),
.CLKB(PORT_B_CLK),
.CEB(PORT_B_CLK_EN),
.WREB(WREB),
.RESETB(RSTB),
.OCEB(1'b0),
.ADB(ADB),
.DIB(DIB),
.DOB(DOB),
);
end else begin
wire [17:0] DIA = PORT_A_WR_DATA;
wire [17:0] DIB = PORT_B_WR_DATA;
wire [17:0] DOA;
wire [17:0] DOB;
assign PORT_A_RD_DATA = DOA;
assign PORT_B_RD_DATA = DOB;
DPX9 #(
`INIT(init_slice_x9)
.READ_MODE0(1'b0),
.READ_MODE1(1'b0),
.WRITE_MODE0(PORT_A_OPTION_WRITE_MODE),
.WRITE_MODE1(PORT_B_OPTION_WRITE_MODE),
.BIT_WIDTH_0(PORT_A_WIDTH),
.BIT_WIDTH_1(PORT_B_WIDTH),
.BLK_SEL(3'b000),
.RESET_MODE(OPTION_RESET_MODE),
) _TECHMAP_REPLACE_ (
.BLKSEL(3'b000),
.CLKA(PORT_A_CLK),
.CEA(PORT_A_CLK_EN),
.WREA(WREA),
.RESETA(RSTA),
.OCEA(1'b0),
.ADA(ADA),
.DIA(DIA),
.DOA(DOA),
.CLKB(PORT_B_CLK),
.CEB(PORT_B_CLK_EN),
.WREB(WREB),
.RESETB(RSTB),
.OCEB(1'b0),
.ADB(ADB),
.DIB(DIB),
.DOB(DOB),
);
end
endgenerate
endmodule
module $__GOWIN_SDP_ (...);
parameter INIT = 0;
parameter OPTION_RESET_MODE = "SYNC";
parameter PORT_R_WIDTH = 18;
parameter PORT_W_WIDTH = 18;
parameter PORT_W_WR_BE_WIDTH = 2;
input PORT_R_CLK;
input PORT_R_CLK_EN;
input PORT_R_RD_SRST;
input PORT_R_RD_ARST;
input [13:0] PORT_R_ADDR;
output [PORT_R_WIDTH-1:0] PORT_R_RD_DATA;
input PORT_W_CLK;
input PORT_W_CLK_EN;
input PORT_W_WR_EN;
input [13:0] PORT_W_ADDR;
input [PORT_W_WR_BE_WIDTH-1:0] PORT_W_WR_BE;
input [PORT_W_WIDTH-1:0] PORT_W_WR_DATA;
`DEF_FUNCS
wire RST = OPTION_RESET_MODE == "SYNC" ? PORT_R_RD_SRST : PORT_R_RD_ARST;
wire WRE = `wre(PORT_W_WIDTH, PORT_W_WR_EN, PORT_W_WR_BE);
wire [13:0] ADW = `addrbe(PORT_W_WIDTH, PORT_W_ADDR, PORT_W_WR_BE);
generate
if (PORT_W_WIDTH < 9 || PORT_R_WIDTH < 9) begin
wire [31:0] DI = `x8_wr_data(PORT_W_WR_DATA);
wire [31:0] DO;
assign PORT_R_RD_DATA = `x8_rd_data(DO);
SDP #(
`INIT(init_slice_x8)
.READ_MODE(1'b0),
.BIT_WIDTH_0(`x8_width(PORT_W_WIDTH)),
.BIT_WIDTH_1(`x8_width(PORT_R_WIDTH)),
.BLK_SEL(3'b000),
.RESET_MODE(OPTION_RESET_MODE),
) _TECHMAP_REPLACE_ (
.BLKSEL(3'b000),
.CLKA(PORT_W_CLK),
.CEA(PORT_W_CLK_EN),
.WREA(WRE),
.RESETA(1'b0),
.ADA(ADW),
.DI(DI),
.CLKB(PORT_R_CLK),
.CEB(PORT_R_CLK_EN),
.WREB(1'b0),
.RESETB(RST),
.OCE(1'b0),
.ADB(PORT_R_ADDR),
.DO(DO),
);
end else begin
wire [35:0] DI = PORT_W_WR_DATA;
wire [35:0] DO;
assign PORT_R_RD_DATA = DO;
SDPX9 #(
`INIT(init_slice_x9)
.READ_MODE(1'b0),
.BIT_WIDTH_0(PORT_W_WIDTH),
.BIT_WIDTH_1(PORT_R_WIDTH),
.BLK_SEL(3'b000),
.RESET_MODE(OPTION_RESET_MODE),
) _TECHMAP_REPLACE_ (
.BLKSEL(3'b000),
.CLKA(PORT_W_CLK),
.CEA(PORT_W_CLK_EN),
.WREA(WRE),
.RESETA(1'b0),
.ADA(ADW),
.DI(DI),
.CLKB(PORT_R_CLK),
.CEB(PORT_R_CLK_EN),
.WREB(1'b0),
.RESETB(RST),
.OCE(1'b0),
.ADB(PORT_R_ADDR),
.DO(DO),
);
end
endgenerate
generate if (CFG_DBITS == 1) begin
SDP #(
`include "bram_init_16.vh"
.READ_MODE(0),
.BIT_WIDTH_0(1),
.BIT_WIDTH_1(1),
.BLK_SEL(3'b000),
.RESET_MODE("SYNC")
) _TECHMAP_REPLACE_ (
.CLKA(CLK2), .CLKB(CLK3),
.WREA(A1EN), .OCE(1'b0), .CEA(1'b1),
.WREB(1'b0), .CEB(B1EN),
.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
.DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
.DO({open, B1DATA}),
.ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}),
.ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
);
end else if (CFG_DBITS == 2) begin
SDP #(
`include "bram_init_16.vh"
.READ_MODE(0),
.BIT_WIDTH_0(2),
.BIT_WIDTH_1(2),
.BLK_SEL(3'b000),
.RESET_MODE("SYNC")
) _TECHMAP_REPLACE_ (
.CLKA(CLK2), .CLKB(CLK3),
.WREA(A1EN), .OCE(1'b0), .CEA(1'b1),
.WREB(1'b0), .CEB(B1EN),
.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
.DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
.DO({open, B1DATA}),
.ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}),
.ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
);
end else if (CFG_DBITS <= 4) begin
SDP #(
`include "bram_init_16.vh"
.READ_MODE(0),
.BIT_WIDTH_0(4),
.BIT_WIDTH_1(4),
.BLK_SEL(3'b000),
.RESET_MODE("SYNC")
) _TECHMAP_REPLACE_ (
.CLKA(CLK2), .CLKB(CLK3),
.WREA(A1EN), .OCE(1'b0),
.WREB(1'b0), .CEB(B1EN), .CEA(1'b1),
.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
.DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
.DO({open, B1DATA}),
.ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}),
.ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
);
end else if (CFG_DBITS <= 8) begin
SDP #(
`include "bram_init_16.vh"
.READ_MODE(0),
.BIT_WIDTH_0(8),
.BIT_WIDTH_1(8),
.BLK_SEL(3'b000),
.RESET_MODE("SYNC")
) _TECHMAP_REPLACE_ (
.CLKA(CLK2), .CLKB(CLK3),
.WREA(A1EN), .OCE(1'b0), .CEA(1'b1),
.WREB(1'b0), .CEB(B1EN),
.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
.DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
.DO({open, B1DATA}),
.ADA({A1ADDR, {(14-CFG_ABITS){1'b0}}}),
.ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
);
end else if (CFG_DBITS <= 16) begin
SDP #(
`include "bram_init_16.vh"
.READ_MODE(0),
.BIT_WIDTH_0(16),
.BIT_WIDTH_1(16),
.BLK_SEL(3'b000),
.RESET_MODE("SYNC")
) _TECHMAP_REPLACE_ (
.CLKA(CLK2), .CLKB(CLK3),
.WREA(|A1EN), .OCE(1'b0),
.WREB(1'b0), .CEB(B1EN), .CEA(1'b1),
.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
.DI({{(32-CFG_DBITS){1'b0}}, A1DATA}),
.DO({open, B1DATA}),
.ADA({A1ADDR, {(12-CFG_ABITS){1'b0}}, A1EN}),
.ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
);
end else if (CFG_DBITS <= 32) begin
SDP #(
`include "bram_init_16.vh"
.READ_MODE(0),
.BIT_WIDTH_0(32),
.BIT_WIDTH_1(32),
.BLK_SEL(3'b000),
.RESET_MODE("SYNC")
) _TECHMAP_REPLACE_ (
.CLKA(CLK2), .CLKB(CLK3),
.WREA(|A1EN), .OCE(1'b0),
.WREB(1'b0), .CEB(B1EN), .CEA(1'b1),
.RESETA(1'b0), .RESETB(1'b0), .BLKSEL(3'b000),
.DI(A1DATA),
.DO(B1DATA),
.ADA({A1ADDR, {(10-CFG_ABITS){1'b0}}, A1EN}),
.ADB({B1ADDR, {(14-CFG_ABITS){1'b0}}})
);
end else begin
wire TECHMAP_FAIL = 1'b1;
end endgenerate
endmodule endmodule

30
techlibs/gowin/lutrams.txt
View File

@ -1,17 +1,13 @@
bram $__GW1NR_RAM16S4 ram distributed $__GOWIN_LUTRAM_ {
init 1 abits 4;
abits 4 width 4;
dbits 4 cost 4;
groups 2 widthscale;
ports 1 1 init no_undef;
wrmode 0 1 prune_rom;
enable 0 1 port sw "W" {
transp 0 1 clock posedge;
clocks 0 1 }
clkpol 0 1 port ar "R" {
endbram }
}
match $__GW1NR_RAM16S4
make_outreg
min wports 1
endmatch

83
techlibs/gowin/lutrams_map.v
View File

@ -1,32 +1,65 @@
module \$__GW1NR_RAM16S4 (CLK1, A1ADDR, A1DATA, A1EN, B1ADDR, B1DATA, B1EN); module $__GOWIN_LUTRAM_(...);
parameter CFG_ABITS = 4;
parameter CFG_DBITS = 4;
parameter [63:0] INIT = 64'bx; parameter INIT = 64'bx;
input CLK1; parameter BITS_USED = 0;
input [CFG_ABITS-1:0] A1ADDR; input PORT_W_CLK;
output [CFG_DBITS-1:0] A1DATA; input [3:0] PORT_W_ADDR;
input A1EN; input PORT_W_WR_EN;
input [3:0] PORT_W_WR_DATA;
input [CFG_ABITS-1:0] B1ADDR; input [3:0] PORT_R_ADDR;
input [CFG_DBITS-1:0] B1DATA; output [3:0] PORT_R_RD_DATA;
input B1EN;
`include "brams_init3.vh" function [15:0] init_slice;
input integer idx;
integer i;
for (i = 0; i < 16; i = i + 1)
init_slice[i] = INIT[4*i+idx];
endfunction
RAM16SDP4 generate
#(.INIT_0(INIT_0),
.INIT_1(INIT_1), casez(BITS_USED)
.INIT_2(INIT_2), 4'b000z:
.INIT_3(INIT_3)) RAM16SDP1 #(
_TECHMAP_REPLACE_ .INIT_0(init_slice(0)),
(.WAD(B1ADDR), ) _TECHMAP_REPLACE_ (
.RAD(A1ADDR), .WAD(PORT_W_ADDR),
.DI(B1DATA), .RAD(PORT_R_ADDR),
.DO(A1DATA), .DI(PORT_W_WR_DATA[0]),
.CLK(CLK1), .DO(PORT_R_RD_DATA[0]),
.WRE(B1EN)); .CLK(PORT_W_CLK),
.WRE(PORT_W_WR_EN)
);
4'b00zz:
RAM16SDP2 #(
.INIT_0(init_slice(0)),
.INIT_1(init_slice(1)),
) _TECHMAP_REPLACE_ (
.WAD(PORT_W_ADDR),
.RAD(PORT_R_ADDR),
.DI(PORT_W_WR_DATA[1:0]),
.DO(PORT_R_RD_DATA[1:0]),
.CLK(PORT_W_CLK),
.WRE(PORT_W_WR_EN)
);
default:
RAM16SDP4 #(
.INIT_0(init_slice(0)),
.INIT_1(init_slice(1)),
.INIT_2(init_slice(2)),
.INIT_3(init_slice(3)),
) _TECHMAP_REPLACE_ (
.WAD(PORT_W_ADDR),
.RAD(PORT_R_ADDR),
.DI(PORT_W_WR_DATA),
.DO(PORT_R_RD_DATA),
.CLK(PORT_W_CLK),
.WRE(PORT_W_WR_EN)
);
endcase
endgenerate
endmodule endmodule

20
techlibs/gowin/synth_gowin.cc
View File

@ -208,17 +208,17 @@ struct SynthGowinPass : public ScriptPass
run("synth -run coarse"); run("synth -run coarse");
} }
if (!nobram && check_label("map_bram", "(skip if -nobram)")) if (check_label("map_ram"))
{ {
run("memory_bram -rules +/gowin/brams.txt"); std::string args = "";
run("techmap -map +/gowin/brams_map.v"); if (nobram)
} args += " -no-auto-block";
if (nolutram)
if (!nolutram && check_label("map_lutram", "(skip if -nolutram)")) args += " -no-auto-distributed";
{ if (help_mode)
run("memory_bram -rules +/gowin/lutrams.txt"); args += " [-no-auto-block] [-no-auto-distributed]";
run("techmap -map +/gowin/lutrams_map.v"); run("memory_libmap -lib +/gowin/lutrams.txt -lib +/gowin/brams.txt" + args, "(-no-auto-block if -nobram, -no-auto-distributed if -nolutram)");
run("setundef -params -zero t:RAM16S4"); run("techmap -map +/gowin/lutrams_map.v -map +/gowin/brams_map.v");
} }
if (check_label("map_ffram")) if (check_label("map_ffram"))