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CodingReadme
35
CodingReadme
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@ -154,6 +154,41 @@ only use one wire from such a group of connected wires. For example:
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log("%d\n", sigmap(a) == sigmap(b)); // will print 1
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Using the RTLIL Netlist Format
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------------------------------
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In the RTLIL netlist format the cell ports contain SigSpecs that point to the
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Wires. There are no references in the other direction. This has two direct
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consequences:
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(1) It is very easy to go from cells to wires but hard to go in the other way.
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(2) There is no danger in removing cells from the netlists, but removing wires
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can break the netlist format when there are still references to the wire
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somewhere in the netlist.
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The solution to (1) is easy: Create custom indexes that allow you to make fast
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lookups for the wire-to-cell direction. You can either use existing generic
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index structures to do that (such as the ModIndex class) or write your own
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index. For many application it is simplest to construct a custom index. For
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example:
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SigMap sigmap(module);
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dict<SigBit, Cell*> sigbit_to_driver_index;
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for (auto cell : module->cells())
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for (auto &conn : cell->connections())
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if (cell->output(conn.first))
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for (auto bit : sigmap(conn.second))
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sigbit_to_driver_index[bit] = cell;
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Regarding (2): There is a general theme in Yosys that you don't remove wires
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from the design. You can rename them, unconnect them, but you do not actually remove
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the Wire object from the module. Instead you let the "clean" command take care
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of the dangling wires. On the other hand it is safe to remove cells (as long as
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you make sure this does not invalidate a custom index you are using in your code).
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Example Code
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------------
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@ -315,7 +315,7 @@ struct WreduceWorker
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};
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struct WreducePass : public Pass {
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WreducePass() : Pass("wreduce", "reduce the word size of operations is possible") { }
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WreducePass() : Pass("wreduce", "reduce the word size of operations if possible") { }
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virtual void help()
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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