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Merge d1eb2e518d into 29e8812bab

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KrystalDelusion 2024-11-26 04:07:22 +13:00 committed by GitHub
parent 29e8812bab d1eb2e518d
commit e462338f17
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4 changed files with 8 additions and 0 deletions
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2
tests/arch/common/blockram.v
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@ -32,6 +32,8 @@ module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
localparam DEPTH = (2**ADDRESS_WIDTH-1);
reg [WORD:0] data_out_r;
(* no_rw_check *)
reg [WORD:0] memory [0:DEPTH];
always @(posedge clk) begin

1
tests/arch/ecp5/memories.ys
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@ -6,6 +6,7 @@ chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp
hierarchy -top sync_ram_sdp
synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 1 t:DP16KD
select -assert-none t:LUT4
## With parameters

3
tests/arch/gatemate/memory.ys
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@ -5,6 +5,9 @@ synth_gatemate -top sync_ram_sdp -noiopad
cd sync_ram_sdp
select -assert-count 1 t:CC_BUFG
select -assert-count 1 t:CC_BRAM_20K
select -assert-none t:CC_LUT3
select -assert-none t:CC_LUT4
select -assert-none t:CC_DFF
# 512 x 20 bit x 2 -> CC_BRAM_20K TDP RAM
design -reset

2
tests/arch/ice40/memories.ys
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@ -6,6 +6,8 @@ chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 2 sync_ram_sdp
hierarchy -top sync_ram_sdp
synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
select -assert-count 1 t:SB_RAM40_4K
select -assert-none t:SB_LUT4
select -assert-none t:SB_DFF
design -reset; read_verilog -defer ../common/blockram.v
chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 4 sync_ram_sdp