Merge d1eb2e518d into 29e8812bab

tests/arch/common/blockram.v

@@ -32,6 +32,8 @@ module sync_ram_sdp #(parameter DATA_WIDTH=8, ADDRESS_WIDTH=10)
   localparam DEPTH = (2**ADDRESS_WIDTH-1);
 
   reg [WORD:0] data_out_r;
+
+  (* no_rw_check *)
   reg [WORD:0] memory [0:DEPTH];
 
   always @(posedge clk) begin

tests/arch/ecp5/memories.ys

@@ -6,6 +6,7 @@ chparam -set ADDRESS_WIDTH 9 -set DATA_WIDTH 36 sync_ram_sdp
 hierarchy -top sync_ram_sdp
 synth_ecp5 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:DP16KD
+select -assert-none t:LUT4
 
 ## With parameters
 

tests/arch/gatemate/memory.ys

@@ -5,6 +5,9 @@ synth_gatemate -top sync_ram_sdp -noiopad
 cd sync_ram_sdp
 select -assert-count 1 t:CC_BUFG
 select -assert-count 1 t:CC_BRAM_20K
+select -assert-none t:CC_LUT3
+select -assert-none t:CC_LUT4
+select -assert-none t:CC_DFF
 
 # 512 x 20 bit x 2 -> CC_BRAM_20K TDP RAM
 design -reset

tests/arch/ice40/memories.ys

@@ -6,6 +6,8 @@ chparam -set ADDRESS_WIDTH 11 -set DATA_WIDTH 2 sync_ram_sdp
 hierarchy -top sync_ram_sdp
 synth_ice40 -top sync_ram_sdp; cd sync_ram_sdp
 select -assert-count 1 t:SB_RAM40_4K
+select -assert-none t:SB_LUT4
+select -assert-none t:SB_DFF
 
 design -reset; read_verilog -defer ../common/blockram.v
 chparam -set ADDRESS_WIDTH 10 -set DATA_WIDTH 4 sync_ram_sdp