riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Enable {* .. *} feature per default (removes dependency to REJECT feature in flex)

This commit is contained in:
Clifford Wolf 2013-11-22 12:46:02 +01:00
parent 18d003254c
commit e4429c480e
5 changed files with 3 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
README
View File

@ -265,8 +265,7 @@ Verilog Attributes and non-standard features
- In addition to the (* ... *) attribute syntax, yosys supports - In addition to the (* ... *) attribute syntax, yosys supports
the non-standard {* ... *} attribute syntax to set default attributes the non-standard {* ... *} attribute syntax to set default attributes
for everything that comes after the {* ... *} statement. (Reset for everything that comes after the {* ... *} statement. (Reset
by adding an empty {* *} statement.) The preprocessor define by adding an empty {* *} statement.)
__YOSYS_ENABLE_DEFATTR__ must be set in order for this feature to be active.
Workarounds for known build problems Workarounds for known build problems

8
frontends/verilog/lexer.l
View File

@ -45,7 +45,6 @@ using namespace VERILOG_FRONTEND;
namespace VERILOG_FRONTEND { namespace VERILOG_FRONTEND {
std::vector<std::string> fn_stack; std::vector<std::string> fn_stack;
std::vector<int> ln_stack; std::vector<int> ln_stack;
bool lexer_feature_defattr;
} }
%} %}
@ -82,9 +81,6 @@ namespace VERILOG_FRONTEND {
"`timescale"[ \t]+[^ \t\r\n/]+[ \t]*"/"[ \t]*[^ \t\r\n]* /* ignore timescale directive */ "`timescale"[ \t]+[^ \t\r\n/]+[ \t]*"/"[ \t]*[^ \t\r\n]* /* ignore timescale directive */
"`yosys_enable_defattr" lexer_feature_defattr = true;
"`yosys_disable_defattr" lexer_feature_defattr = false;
"`"[a-zA-Z_$][a-zA-Z0-9_$]* { "`"[a-zA-Z_$][a-zA-Z0-9_$]* {
frontend_verilog_yyerror("Unimplemented compiler directive or undefined macro %s.", yytext); frontend_verilog_yyerror("Unimplemented compiler directive or undefined macro %s.", yytext);
} }
@ -225,8 +221,8 @@ supply1 { return TOK_SUPPLY1; }
"(*" { return ATTR_BEGIN; } "(*" { return ATTR_BEGIN; }
"*)" { return ATTR_END; } "*)" { return ATTR_END; }
"{*" { if (lexer_feature_defattr) return DEFATTR_BEGIN; else REJECT; } "{*" { return DEFATTR_BEGIN; }
"*}" { if (lexer_feature_defattr) return DEFATTR_END; else REJECT; } "*}" { return DEFATTR_END; }
"**" { return OP_POW; } "**" { return OP_POW; }
"||" { return OP_LOR; } "||" { return OP_LOR; }

11
frontends/verilog/preproc.cc
View File

@ -198,13 +198,6 @@ static void input_file(FILE *f, std::string filename)
input_buffer.insert(it, "`file_pop\n"); input_buffer.insert(it, "`file_pop\n");
} }
static std::string define_to_feature(std::string defname)
{
if (defname == "__YOSYS_ENABLE_DEFATTR__")
return "defattr";
return std::string();
}
std::string frontend_verilog_preproc(FILE *f, std::string filename, const std::map<std::string, std::string> pre_defines_map, const std::list<std::string> include_dirs) std::string frontend_verilog_preproc(FILE *f, std::string filename, const std::map<std::string, std::string> pre_defines_map, const std::list<std::string> include_dirs)
{ {
std::map<std::string, std::string> defines_map(pre_defines_map); std::map<std::string, std::string> defines_map(pre_defines_map);
@ -298,8 +291,6 @@ std::string frontend_verilog_preproc(FILE *f, std::string filename, const std::m
std::string name, value; std::string name, value;
skip_spaces(); skip_spaces();
name = next_token(true); name = next_token(true);
if (!define_to_feature(name).empty())
output_code.push_back("`yosys_enable_" + define_to_feature(name));
skip_spaces(); skip_spaces();
int newline_count = 0; int newline_count = 0;
while (!tok.empty()) { while (!tok.empty()) {
@ -331,8 +322,6 @@ std::string frontend_verilog_preproc(FILE *f, std::string filename, const std::m
std::string name; std::string name;
skip_spaces(); skip_spaces();
name = next_token(true); name = next_token(true);
if (!define_to_feature(name).empty())
output_code.push_back("`yosys_disable_" + define_to_feature(name));
// printf("undef: >>%s<<\n", name.c_str()); // printf("undef: >>%s<<\n", name.c_str());
defines_map.erase(name); defines_map.erase(name);
continue; continue;

2
frontends/verilog/verilog_frontend.cc
View File

@ -206,8 +206,6 @@ struct VerilogFrontend : public Frontend {
fp = fmemopen((void*)code_after_preproc.c_str(), code_after_preproc.size(), "r"); fp = fmemopen((void*)code_after_preproc.c_str(), code_after_preproc.size(), "r");
} }
lexer_feature_defattr = false;
frontend_verilog_yyset_lineno(1); frontend_verilog_yyset_lineno(1);
frontend_verilog_yyrestart(fp); frontend_verilog_yyrestart(fp);
frontend_verilog_yyparse(); frontend_verilog_yyparse();

3
frontends/verilog/verilog_frontend.h
View File

@ -42,9 +42,6 @@ namespace VERILOG_FRONTEND
// this function converts a Verilog constant to an AST_CONSTANT node // this function converts a Verilog constant to an AST_CONSTANT node
AST::AstNode *const2ast(std::string code, char case_type = 0); AST::AstNode *const2ast(std::string code, char case_type = 0);
// lexer state variables
extern bool lexer_feature_defattr;
} }
// the pre-processor // the pre-processor