mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #4779 from YosysHQ/emil/han-carlson-adder
Add a Han-Carlson option for `$lcu` mapping
This commit is contained in:
commit
e436cc053f
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@ -36,3 +36,4 @@ $(eval $(call add_share_file,share,techlibs/common/abc9_unmap.v))
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$(eval $(call add_share_file,share,techlibs/common/cmp2lcu.v))
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$(eval $(call add_share_file,share,techlibs/common/cmp2softlogic.v))
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$(eval $(call add_share_file,share/choices,techlibs/common/choices/kogge-stone.v))
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$(eval $(call add_share_file,share/choices,techlibs/common/choices/han-carlson.v))
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@ -0,0 +1,57 @@
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(* techmap_celltype = "$lcu" *)
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module _80_lcu_han_carlson (P, G, CI, CO);
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parameter WIDTH = 2;
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(* force_downto *)
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input [WIDTH-1:0] P, G;
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input CI;
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(* force_downto *)
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output [WIDTH-1:0] CO;
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integer i, j;
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(* force_downto *)
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reg [WIDTH-1:0] p, g;
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always @* begin
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i = 0;
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p = P;
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g = G;
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// in almost all cases CI will be constant zero
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g[0] = g[0] | (p[0] & CI);
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if (i < $clog2(WIDTH)) begin
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// First layer: BK
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for (j = WIDTH - 1; j >= 0; j = j - 1) begin
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if (j % 2 == 1) begin
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g[j] = g[j] | p[j] & g[j - 1];
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p[j] = p[j] & p[j - 1];
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end
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end
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// Inner (log(WIDTH) - 1) layers: KS
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for (i = 1; i < $clog2(WIDTH); i = i + 1) begin
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for (j = WIDTH - 1; j >= 2**i; j = j - 1) begin
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if (j % 2 == 1) begin
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g[j] = g[j] | p[j] & g[j - 2**i];
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p[j] = p[j] & p[j - 2**i];
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end
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end
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end
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// Last layer: BK
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if (i < ($clog2(WIDTH) + 1)) begin
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for (j = WIDTH - 1; j >= 0; j = j - 1) begin
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if ((j % 2 == 0) && (j > 0)) begin
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g[j] = g[j] | p[j] & g[j - 1];
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p[j] = p[j] & p[j - 1];
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end
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end
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end
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end
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end
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assign CO = g;
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endmodule
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@ -20,6 +20,13 @@ generate_ys_test() {
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generate_target "$ys_file" "\"$YOSYS_BASEDIR/yosys\" -ql ${ys_file%.*}.log $yosys_args_ $ys_file"
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}
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# $ generate_tcl_test tcl_file [yosys_args]
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generate_tcl_test() {
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tcl_file=$1
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yosys_args_=${2:-}
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generate_target "$tcl_file" "\"$YOSYS_BASEDIR/yosys\" -ql ${tcl_file%.*}.log $yosys_args_ $tcl_file"
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}
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# $ generate_bash_test bash_file
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generate_bash_test() {
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bash_file=$1
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@ -29,6 +36,7 @@ generate_bash_test() {
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# $ generate_tests [-y|--yosys-scripts] [-s|--prove-sv] [-b|--bash] [-a|--yosys-args yosys_args]
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generate_tests() {
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do_ys=false
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do_tcl=false
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do_sv=false
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do_sh=false
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yosys_args=""
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@ -40,6 +48,10 @@ generate_tests() {
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do_ys=true
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shift
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;;
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-t|--tcl-scripts)
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do_tcl=true
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shift
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;;
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-s|--prove-sv)
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do_sv=true
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shift
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@ -59,7 +71,7 @@ generate_tests() {
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esac
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done
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if [[ ! ( $do_ys = true || $do_sv = true || $do_sh = true ) ]]; then
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if [[ ! ( $do_ys = true || $do_tcl = true || $do_sv = true || $do_sh = true ) ]]; then
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echo >&2 "Error: No file types selected"
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exit 1
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fi
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@ -72,6 +84,11 @@ generate_tests() {
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generate_ys_test "$x" "$yosys_args"
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done
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fi;
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if [[ $do_tcl = true ]]; then
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for x in *.tcl; do
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generate_tcl_test "$x" "$yosys_args"
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done
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fi;
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if [[ $do_sv = true ]]; then
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for x in *.sv; do
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if [ ! -f "${x%.sv}.ys" ]; then
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@ -0,0 +1,15 @@
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yosys -import
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read_verilog +/choices/han-carlson.v
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read_verilog -icells lcu_refined.v
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design -save init
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for {set i 1} {$i <= 16} {incr i} {
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design -load init
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chparam -set WIDTH $i
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yosys proc
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opt_clean
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equiv_make lcu _80_lcu_han_carlson equiv
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equiv_simple equiv
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equiv_status -assert equiv
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}
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@ -0,0 +1,15 @@
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yosys -import
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read_verilog +/choices/kogge-stone.v
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read_verilog -icells lcu_refined.v
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design -save init
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for {set i 1} {$i <= 16} {incr i} {
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design -load init
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chparam -set WIDTH $i
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yosys proc
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opt_clean
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equiv_make lcu _80_lcu_kogge_stone equiv
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equiv_simple equiv
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equiv_status -assert equiv
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}
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@ -1 +0,0 @@
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test_cell -s 1711533949 -n 10 -map +/techmap.v -map +/choices/kogge-stone.v $lcu
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@ -0,0 +1,13 @@
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module lcu (P, G, CI, CO);
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parameter WIDTH = 2;
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input [WIDTH-1:0] P, G;
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input CI;
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output [WIDTH-1:0] CO;
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reg [WIDTH-1:0] p, g;
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\$lcu #(.WIDTH(WIDTH)) impl (.P(P), .G(G), .CI(CI), .CO(CO));
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endmodule
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@ -1,4 +1,4 @@
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#!/usr/bin/env bash
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set -eu
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source ../gen-tests-makefile.sh
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run_tests --yosys-scripts --bash --yosys-args "-e 'select out of bounds'"
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run_tests --yosys-scripts --tcl-scripts --bash --yosys-args "-e 'select out of bounds'"
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