mirror of https://github.com/YosysHQ/yosys.git
Use IdString::begins_with()
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@ -297,7 +297,7 @@ struct FirrtlWorker
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std::string cell_type = fid(cell->type);
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std::string instanceOf;
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// If this is a parameterized module, its parent module is encoded in the cell type
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if (cell->type.substr(0, 8) == "$paramod")
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if (cell->type.begins_with("$paramod"))
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{
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std::string::iterator it;
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for (it = cell_type.begin(); it < cell_type.end(); it++)
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@ -776,7 +776,7 @@ struct FirrtlWorker
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}
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// This may be a parameterized module - paramod.
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if (cell->type.substr(0, 8) == "$paramod")
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if (cell->type.begins_with("$paramod"))
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{
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process_instance(cell, wire_exprs);
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continue;
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@ -828,8 +828,8 @@ namespace {
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void check()
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{
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if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" || cell->type.substr(0,10) == "$fmcombine" ||
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cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:")
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if (cell->type.begins_with("$") || cell->type.begins_with("$__") || cell->type.begins_with("$paramod") || cell->type.begins_with("$fmcombine") ||
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cell->type.begins_with("$verific$") || cell->type.begins_with("$array:") || cell->type.begins_with("$extern:"))
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return;
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if (cell->type.in("$not", "$pos", "$neg")) {
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@ -2553,8 +2553,8 @@ void RTLIL::Cell::check()
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void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
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{
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if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" || type.substr(0,10) == "$fmcombine" ||
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type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:")
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if (type.begins_with("$") || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") ||
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type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:"))
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return;
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if (type == "$mux" || type == "$pmux") {
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@ -276,20 +276,24 @@ namespace RTLIL
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return std::string(c_str() + pos, len);
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}
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int compare(size_t pos, size_t len, const char* s) const {
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return strncmp(c_str()+pos, s, len);
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}
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bool begins_with(const char* prefix) const {
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size_t len = strlen(prefix);
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if (size() < len) return false;
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return substr(0, len) == prefix;
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return compare(0, len, prefix);
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}
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bool ends_with(const char* suffix) const {
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size_t len = strlen(suffix);
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if (size() < len) return false;
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return substr(size()-len) == suffix;
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return compare(size()-len, len, suffix);
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}
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size_t size() const {
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return str().size();
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return strlen(c_str());
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}
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bool empty() const {
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@ -48,7 +48,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
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RTLIL::Cell *cell = i2.second;
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if (design->has(cell->type))
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continue;
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if (cell->type.substr(0, 1) == "$" && cell->type.substr(0, 3) != "$__")
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if (cell->type.begins_with("$__"))
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continue;
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for (auto &pattern : celltypes)
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if (patmatch(pattern.c_str(), RTLIL::unescape_id(cell->type).c_str()))
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@ -143,7 +143,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
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// Return the "basic" type for an array item.
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std::string basic_cell_type(const std::string celltype, int pos[3] = nullptr) {
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std::string basicType = celltype;
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if (celltype.substr(0, 7) == "$array:") {
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if (celltype.compare(0, strlen("$array:"), "$array:")) {
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int pos_idx = celltype.find_first_of(':');
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int pos_num = celltype.find_first_of(':', pos_idx + 1);
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int pos_type = celltype.find_first_of(':', pos_num + 1);
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@ -194,14 +194,14 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
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std::vector<RTLIL::IdString> connections_to_add_name;
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std::vector<RTLIL::SigSpec> connections_to_add_signal;
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if (cell->type.substr(0, 7) == "$array:") {
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if (cell->type.begins_with("$array:")) {
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int pos[3];
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basic_cell_type(cell->type.str(), pos);
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int pos_idx = pos[0];
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int pos_num = pos[1];
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int pos_type = pos[2];
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int idx = atoi(cell->type.str().substr(pos_idx + 1, pos_num).c_str());
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int num = atoi(cell->type.str().substr(pos_num + 1, pos_type).c_str());
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int idx = std::stoi(cell->type.str().substr(pos_idx + 1, pos_num));
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int num = std::stoi(cell->type.str().substr(pos_num + 1, pos_type));
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array_cells[cell] = std::pair<int, int>(idx, num);
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cell->type = cell->type.str().substr(pos_type + 1);
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}
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@ -422,8 +422,8 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
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for (auto &conn : cell->connections_) {
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int conn_size = conn.second.size();
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RTLIL::IdString portname = conn.first;
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if (portname.substr(0, 1) == "$") {
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int port_id = atoi(portname.substr(1).c_str());
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if (portname.begins_with("$")) {
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int port_id = std::stoi(portname.substr(1));
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for (auto &wire_it : mod->wires_)
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if (wire_it.second->port_id == port_id) {
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portname = wire_it.first;
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@ -457,9 +457,8 @@ void hierarchy_worker(RTLIL::Design *design, std::set<RTLIL::Module*, IdString::
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for (auto cell : mod->cells()) {
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std::string celltype = cell->type.str();
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if (celltype.substr(0, 7) == "$array:") {
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if (celltype.compare(0, strlen("$array:"), "$array:"))
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celltype = basic_cell_type(celltype);
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}
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if (design->module(celltype))
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hierarchy_worker(design, used, design->module(celltype), indent+4);
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}
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@ -521,9 +520,8 @@ int find_top_mod_score(Design *design, Module *module, dict<Module*, int> &db)
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for (auto cell : module->cells()) {
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std::string celltype = cell->type.str();
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// Is this an array instance
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if (celltype.substr(0, 7) == "$array:") {
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if (celltype.compare(0, strlen("$array:"), "$array:"))
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celltype = basic_cell_type(celltype);
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}
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// Is this cell a module instance?
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auto instModule = design->module(celltype);
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// If there is no instance for this, issue a warning.
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@ -63,11 +63,11 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
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log_assert(GetSize(sig_set) == GetSize(sig_clr));
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if (cell->type.substr(0,8) == "$_DFFSR_") {
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if (cell->type.begins_with("$_DFFSR_")) {
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pol_set = cell->type[9] == 'P' ? State::S1 : State::S0;
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pol_clr = cell->type[10] == 'P' ? State::S1 : State::S0;
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} else
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if (cell->type.substr(0,11) == "$_DLATCHSR_") {
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if (cell->type.begins_with("$_DLATCHSR_")) {
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pol_set = cell->type[12] == 'P' ? State::S1 : State::S0;
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pol_clr = cell->type[13] == 'P' ? State::S1 : State::S0;
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} else
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@ -198,9 +198,9 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
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{
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IdString new_type;
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if (cell->type.substr(0,8) == "$_DFFSR_")
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if (cell->type.begins_with("$_DFFSR_"))
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new_type = stringf("$_DFF_%c_", cell->type[8]);
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else if (cell->type.substr(0,11) == "$_DLATCHSR_")
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else if (cell->type.begins_with("$_DLATCHSR_"))
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new_type = stringf("$_DLATCH_%c_", cell->type[11]);
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else
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log_abort();
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@ -278,7 +278,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
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sig_c = dff->getPort("\\C");
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val_cp = RTLIL::Const(dff->type == "$_DFF_P_", 1);
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}
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else if (dff->type.substr(0,6) == "$_DFF_" && dff->type.substr(9) == "_" &&
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else if (dff->type.begins_with("$_DFF_") && dff->type.substr(9) == "_" &&
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(dff->type[6] == 'N' || dff->type[6] == 'P') &&
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(dff->type[7] == 'N' || dff->type[7] == 'P') &&
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(dff->type[8] == '0' || dff->type[8] == '1')) {
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@ -290,7 +290,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
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val_rp = RTLIL::Const(dff->type[7] == 'P', 1);
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val_rv = RTLIL::Const(dff->type[8] == '1', 1);
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}
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else if (dff->type.substr(0,7) == "$_DFFE_" && dff->type.substr(9) == "_" &&
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else if (dff->type.begins_with("$_DFFE_") && dff->type.substr(9) == "_" &&
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(dff->type[7] == 'N' || dff->type[7] == 'P') &&
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(dff->type[8] == 'N' || dff->type[8] == 'P')) {
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sig_d = dff->getPort("\\D");
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@ -428,7 +428,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
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return true;
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}
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log_assert(dff->type.substr(0,6) == "$_DFF_");
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log_assert(dff->type.begins_with("$_DFF_"));
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dff->type = stringf("$_DFF_%c_", + dff->type[6]);
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dff->unsetPort("\\R");
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}
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@ -452,7 +452,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
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return true;
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}
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log_assert(dff->type.substr(0,7) == "$_DFFE_");
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log_assert(dff->type.begins_with("$_DFFE_"));
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dff->type = stringf("$_DFF_%c_", + dff->type[7]);
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dff->unsetPort("\\E");
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}
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