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Use IdString::begins_with()

This commit is contained in:
Eddie Hung 2019-08-06 16:42:25 -07:00
parent a6bc9265fb
commit e38f40af5b
5 changed files with 30 additions and 28 deletions
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4
backends/firrtl/firrtl.cc
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@ -297,7 +297,7 @@ struct FirrtlWorker
std::string cell_type = fid(cell->type); std::string cell_type = fid(cell->type);
std::string instanceOf; std::string instanceOf;
// If this is a parameterized module, its parent module is encoded in the cell type // If this is a parameterized module, its parent module is encoded in the cell type
if (cell->type.substr(0, 8) == "$paramod") if (cell->type.begins_with("$paramod"))
{ {
std::string::iterator it; std::string::iterator it;
for (it = cell_type.begin(); it < cell_type.end(); it++) for (it = cell_type.begin(); it < cell_type.end(); it++)
@ -776,7 +776,7 @@ struct FirrtlWorker
} }
// This may be a parameterized module - paramod. // This may be a parameterized module - paramod.
if (cell->type.substr(0, 8) == "$paramod") if (cell->type.begins_with("$paramod"))
{ {
process_instance(cell, wire_exprs); process_instance(cell, wire_exprs);
continue; continue;

8
kernel/rtlil.cc
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@ -828,8 +828,8 @@ namespace {
void check() void check()
{ {
if (cell->type.substr(0, 1) != "$" || cell->type.substr(0, 3) == "$__" || cell->type.substr(0, 8) == "$paramod" || cell->type.substr(0,10) == "$fmcombine" || if (cell->type.begins_with("$") || cell->type.begins_with("$__") || cell->type.begins_with("$paramod") || cell->type.begins_with("$fmcombine") ||
cell->type.substr(0, 9) == "$verific$" || cell->type.substr(0, 7) == "$array:" || cell->type.substr(0, 8) == "$extern:") cell->type.begins_with("$verific$") || cell->type.begins_with("$array:") || cell->type.begins_with("$extern:"))
return; return;
if (cell->type.in("$not", "$pos", "$neg")) { if (cell->type.in("$not", "$pos", "$neg")) {
@ -2553,8 +2553,8 @@ void RTLIL::Cell::check()
void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed) void RTLIL::Cell::fixup_parameters(bool set_a_signed, bool set_b_signed)
{ {
if (type.substr(0, 1) != "$" || type.substr(0, 2) == "$_" || type.substr(0, 8) == "$paramod" || type.substr(0,10) == "$fmcombine" || if (type.begins_with("$") || type.begins_with("$_") || type.begins_with("$paramod") || type.begins_with("$fmcombine") ||
type.substr(0, 9) == "$verific$" || type.substr(0, 7) == "$array:" || type.substr(0, 8) == "$extern:") type.begins_with("$verific$") || type.begins_with("$array:") || type.begins_with("$extern:"))
return; return;
if (type == "$mux" || type == "$pmux") { if (type == "$mux" || type == "$pmux") {

10
kernel/rtlil.h
View File

@ -276,20 +276,24 @@ namespace RTLIL
return std::string(c_str() + pos, len); return std::string(c_str() + pos, len);
} }
int compare(size_t pos, size_t len, const char* s) const {
return strncmp(c_str()+pos, s, len);
}
bool begins_with(const char* prefix) const { bool begins_with(const char* prefix) const {
size_t len = strlen(prefix); size_t len = strlen(prefix);
if (size() < len) return false; if (size() < len) return false;
return substr(0, len) == prefix; return compare(0, len, prefix);
} }
bool ends_with(const char* suffix) const { bool ends_with(const char* suffix) const {
size_t len = strlen(suffix); size_t len = strlen(suffix);
if (size() < len) return false; if (size() < len) return false;
return substr(size()-len) == suffix; return compare(size()-len, len, suffix);
} }
size_t size() const { size_t size() const {
return str().size(); return strlen(c_str());
} }
bool empty() const { bool empty() const {

20
passes/hierarchy/hierarchy.cc
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@ -48,7 +48,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
RTLIL::Cell *cell = i2.second; RTLIL::Cell *cell = i2.second;
if (design->has(cell->type)) if (design->has(cell->type))
continue; continue;
if (cell->type.substr(0, 1) == "$" && cell->type.substr(0, 3) != "$__") if (cell->type.begins_with("$__"))
continue; continue;
for (auto &pattern : celltypes) for (auto &pattern : celltypes)
if (patmatch(pattern.c_str(), RTLIL::unescape_id(cell->type).c_str())) if (patmatch(pattern.c_str(), RTLIL::unescape_id(cell->type).c_str()))
@ -143,7 +143,7 @@ void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes,
// Return the "basic" type for an array item. // Return the "basic" type for an array item.
std::string basic_cell_type(const std::string celltype, int pos[3] = nullptr) { std::string basic_cell_type(const std::string celltype, int pos[3] = nullptr) {
std::string basicType = celltype; std::string basicType = celltype;
if (celltype.substr(0, 7) == "$array:") { if (celltype.compare(0, strlen("$array:"), "$array:")) {
int pos_idx = celltype.find_first_of(':'); int pos_idx = celltype.find_first_of(':');
int pos_num = celltype.find_first_of(':', pos_idx + 1); int pos_num = celltype.find_first_of(':', pos_idx + 1);
int pos_type = celltype.find_first_of(':', pos_num + 1); int pos_type = celltype.find_first_of(':', pos_num + 1);
@ -194,14 +194,14 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
std::vector<RTLIL::IdString> connections_to_add_name; std::vector<RTLIL::IdString> connections_to_add_name;
std::vector<RTLIL::SigSpec> connections_to_add_signal; std::vector<RTLIL::SigSpec> connections_to_add_signal;
if (cell->type.substr(0, 7) == "$array:") { if (cell->type.begins_with("$array:")) {
int pos[3]; int pos[3];
basic_cell_type(cell->type.str(), pos); basic_cell_type(cell->type.str(), pos);
int pos_idx = pos[0]; int pos_idx = pos[0];
int pos_num = pos[1]; int pos_num = pos[1];
int pos_type = pos[2]; int pos_type = pos[2];
int idx = atoi(cell->type.str().substr(pos_idx + 1, pos_num).c_str()); int idx = std::stoi(cell->type.str().substr(pos_idx + 1, pos_num));
int num = atoi(cell->type.str().substr(pos_num + 1, pos_type).c_str()); int num = std::stoi(cell->type.str().substr(pos_num + 1, pos_type));
array_cells[cell] = std::pair<int, int>(idx, num); array_cells[cell] = std::pair<int, int>(idx, num);
cell->type = cell->type.str().substr(pos_type + 1); cell->type = cell->type.str().substr(pos_type + 1);
} }
@ -422,8 +422,8 @@ bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool flag_check
for (auto &conn : cell->connections_) { for (auto &conn : cell->connections_) {
int conn_size = conn.second.size(); int conn_size = conn.second.size();
RTLIL::IdString portname = conn.first; RTLIL::IdString portname = conn.first;
if (portname.substr(0, 1) == "$") { if (portname.begins_with("$")) {
int port_id = atoi(portname.substr(1).c_str()); int port_id = std::stoi(portname.substr(1));
for (auto &wire_it : mod->wires_) for (auto &wire_it : mod->wires_)
if (wire_it.second->port_id == port_id) { if (wire_it.second->port_id == port_id) {
portname = wire_it.first; portname = wire_it.first;
@ -457,9 +457,8 @@ void hierarchy_worker(RTLIL::Design *design, std::set<RTLIL::Module*, IdString::
for (auto cell : mod->cells()) { for (auto cell : mod->cells()) {
std::string celltype = cell->type.str(); std::string celltype = cell->type.str();
if (celltype.substr(0, 7) == "$array:") { if (celltype.compare(0, strlen("$array:"), "$array:"))
celltype = basic_cell_type(celltype); celltype = basic_cell_type(celltype);
}
if (design->module(celltype)) if (design->module(celltype))
hierarchy_worker(design, used, design->module(celltype), indent+4); hierarchy_worker(design, used, design->module(celltype), indent+4);
} }
@ -521,9 +520,8 @@ int find_top_mod_score(Design *design, Module *module, dict<Module*, int> &db)
for (auto cell : module->cells()) { for (auto cell : module->cells()) {
std::string celltype = cell->type.str(); std::string celltype = cell->type.str();
// Is this an array instance // Is this an array instance
if (celltype.substr(0, 7) == "$array:") { if (celltype.compare(0, strlen("$array:"), "$array:"))
celltype = basic_cell_type(celltype); celltype = basic_cell_type(celltype);
}
// Is this cell a module instance? // Is this cell a module instance?
auto instModule = design->module(celltype); auto instModule = design->module(celltype);
// If there is no instance for this, issue a warning. // If there is no instance for this, issue a warning.

16
passes/opt/opt_rmdff.cc
View File

@ -63,11 +63,11 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
log_assert(GetSize(sig_set) == GetSize(sig_clr)); log_assert(GetSize(sig_set) == GetSize(sig_clr));
if (cell->type.substr(0,8) == "$_DFFSR_") { if (cell->type.begins_with("$_DFFSR_")) {
pol_set = cell->type[9] == 'P' ? State::S1 : State::S0; pol_set = cell->type[9] == 'P' ? State::S1 : State::S0;
pol_clr = cell->type[10] == 'P' ? State::S1 : State::S0; pol_clr = cell->type[10] == 'P' ? State::S1 : State::S0;
} else } else
if (cell->type.substr(0,11) == "$_DLATCHSR_") { if (cell->type.begins_with("$_DLATCHSR_")) {
pol_set = cell->type[12] == 'P' ? State::S1 : State::S0; pol_set = cell->type[12] == 'P' ? State::S1 : State::S0;
pol_clr = cell->type[13] == 'P' ? State::S1 : State::S0; pol_clr = cell->type[13] == 'P' ? State::S1 : State::S0;
} else } else
@ -198,9 +198,9 @@ bool handle_dffsr(RTLIL::Module *mod, RTLIL::Cell *cell)
{ {
IdString new_type; IdString new_type;
if (cell->type.substr(0,8) == "$_DFFSR_") if (cell->type.begins_with("$_DFFSR_"))
new_type = stringf("$_DFF_%c_", cell->type[8]); new_type = stringf("$_DFF_%c_", cell->type[8]);
else if (cell->type.substr(0,11) == "$_DLATCHSR_") else if (cell->type.begins_with("$_DLATCHSR_"))
new_type = stringf("$_DLATCH_%c_", cell->type[11]); new_type = stringf("$_DLATCH_%c_", cell->type[11]);
else else
log_abort(); log_abort();
@ -278,7 +278,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
sig_c = dff->getPort("\\C"); sig_c = dff->getPort("\\C");
val_cp = RTLIL::Const(dff->type == "$_DFF_P_", 1); val_cp = RTLIL::Const(dff->type == "$_DFF_P_", 1);
} }
else if (dff->type.substr(0,6) == "$_DFF_" && dff->type.substr(9) == "_" && else if (dff->type.begins_with("$_DFF_") && dff->type.substr(9) == "_" &&
(dff->type[6] == 'N' || dff->type[6] == 'P') && (dff->type[6] == 'N' || dff->type[6] == 'P') &&
(dff->type[7] == 'N' || dff->type[7] == 'P') && (dff->type[7] == 'N' || dff->type[7] == 'P') &&
(dff->type[8] == '0' || dff->type[8] == '1')) { (dff->type[8] == '0' || dff->type[8] == '1')) {
@ -290,7 +290,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
val_rp = RTLIL::Const(dff->type[7] == 'P', 1); val_rp = RTLIL::Const(dff->type[7] == 'P', 1);
val_rv = RTLIL::Const(dff->type[8] == '1', 1); val_rv = RTLIL::Const(dff->type[8] == '1', 1);
} }
else if (dff->type.substr(0,7) == "$_DFFE_" && dff->type.substr(9) == "_" && else if (dff->type.begins_with("$_DFFE_") && dff->type.substr(9) == "_" &&
(dff->type[7] == 'N' || dff->type[7] == 'P') && (dff->type[7] == 'N' || dff->type[7] == 'P') &&
(dff->type[8] == 'N' || dff->type[8] == 'P')) { (dff->type[8] == 'N' || dff->type[8] == 'P')) {
sig_d = dff->getPort("\\D"); sig_d = dff->getPort("\\D");
@ -428,7 +428,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
return true; return true;
} }
log_assert(dff->type.substr(0,6) == "$_DFF_"); log_assert(dff->type.begins_with("$_DFF_"));
dff->type = stringf("$_DFF_%c_", + dff->type[6]); dff->type = stringf("$_DFF_%c_", + dff->type[6]);
dff->unsetPort("\\R"); dff->unsetPort("\\R");
} }
@ -452,7 +452,7 @@ bool handle_dff(RTLIL::Module *mod, RTLIL::Cell *dff)
return true; return true;
} }
log_assert(dff->type.substr(0,7) == "$_DFFE_"); log_assert(dff->type.begins_with("$_DFFE_"));
dff->type = stringf("$_DFF_%c_", + dff->type[7]); dff->type = stringf("$_DFF_%c_", + dff->type[7]);
dff->unsetPort("\\E"); dff->unsetPort("\\E");
} }