mirror of https://github.com/YosysHQ/yosys.git
Revert "Fix sign extension when sign is 1'bx"
This reverts commit 0221f3e1c5
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@ -3437,7 +3437,7 @@ void RTLIL::SigSpec::extend_u0(int width, bool is_signed)
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if (width_ < width) {
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if (width_ < width) {
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RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
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RTLIL::SigBit padding = width_ > 0 ? (*this)[width_ - 1] : RTLIL::State::Sx;
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if (padding != RTLIL::State::Sx && !is_signed)
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if (!is_signed)
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padding = RTLIL::State::S0;
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padding = RTLIL::State::S0;
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while (width_ < width)
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while (width_ < width)
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append(padding);
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append(padding);
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