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Update README
Signed-off-by: Clifford Wolf <clifford@clifford.at>
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@ -259,11 +259,7 @@ for them:
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- The ``tri``, ``triand``, ``trior``, ``wand`` and ``wor`` net types
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- The ``tri``, ``triand``, ``trior``, ``wand`` and ``wor`` net types
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- The ``config`` keyword and library map files
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- The ``config`` and ``disable`` keywords and library map files
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- The ``disable``, ``primitive`` and ``specify`` statements
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- Latched logic (is synthesized as logic with feedback loops)
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Verilog Attributes and non-standard features
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Verilog Attributes and non-standard features
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