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Update README 

Signed-off-by: Clifford Wolf <clifford@clifford.at>
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Clifford Wolf 2019-05-04 08:01:39 +02:00
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@ -259,11 +259,7 @@ for them:
- The ``tri``, ``triand``, ``trior``, ``wand`` and ``wor`` net types - The ``tri``, ``triand``, ``trior``, ``wand`` and ``wor`` net types
- The ``config`` keyword and library map files - The ``config`` and ``disable`` keywords and library map files
- The ``disable``, ``primitive`` and ``specify`` statements
- Latched logic (is synthesized as logic with feedback loops)
Verilog Attributes and non-standard features Verilog Attributes and non-standard features