Make one check $shift(x)? only; change testcase to be 8b

This commit is contained in:
Eddie Hung 2019-09-06 22:48:23 -07:00
parent 51b559af2c
commit e2c2d784c8
2 changed files with 5 additions and 4 deletions

View File

@ -50,6 +50,7 @@ code
if (GetSize(const_factor_cnst) > 20) if (GetSize(const_factor_cnst) > 20)
reject; reject;
if (shift->type.in($shift, $shiftx))
if (GetSize(port(shift, \Y)) > const_factor) if (GetSize(port(shift, \Y)) > const_factor)
reject; reject;

View File

@ -16,7 +16,7 @@ select -assert-count 0 t:$shiftx t:* %D
design -reset design -reset
read_verilog <<EOT read_verilog <<EOT
module peepopt_shiftmul_1 (output [7:0] y, input [2:0] w); module peepopt_shiftmul_1 (output [7:0] y, input [2:0] w);
assign y = 1'b1 >> (w * (3'b110)); assign y = 1'b1 >> (w * (8'b110));
endmodule endmodule
EOT EOT
@ -25,7 +25,7 @@ equiv_opt -assert peepopt
design -load postopt design -load postopt
clean clean
select -assert-count 1 t:$shr select -assert-count 1 t:$shr
select -assert-count 1 t:$mul select -assert-count 0 t:$mul
select -assert-count 0 t:$shr t:$mul %% t:* %D select -assert-count 0 t:$shr t:$mul %% t:* %D
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