diff --git a/docs/source/appendix/APPNOTE_011_Design_Investigation.rst b/docs/source/appendix/APPNOTE_011_Design_Investigation.rst index 3adcc4913..698f2da2c 100644 --- a/docs/source/appendix/APPNOTE_011_Design_Investigation.rst +++ b/docs/source/appendix/APPNOTE_011_Design_Investigation.rst @@ -78,10 +78,10 @@ A simple circuit :numref:`example_src` shows a simple synthesis script and a Verilog file that demonstrate the usage of show in a simple setting. Note that :cmd:ref:`show` is -called with the :cmd:ref:`-pause` option, that halts execution of the Yosys -script until the user presses the Enter key. The ``show -pause`` command also -allows the user to enter an interactive shell to further investigate the circuit -before continuing synthesis. +called with the ``-pause`` option, that halts execution of the Yosys script +until the user presses the Enter key. The ``show -pause`` command also allows +the user to enter an interactive shell to further investigate the circuit before +continuing synthesis. So this script, when executed, will show the design after each of the three synthesis commands. The generated circuit diagrams are shown in diff --git a/docs/source/getting_started/index.rst b/docs/source/getting_started/index.rst index e53e344d8..0828adf39 100644 --- a/docs/source/getting_started/index.rst +++ b/docs/source/getting_started/index.rst @@ -2,6 +2,7 @@ Getting started with Yosys ========================== .. toctree:: + :maxdepth: 3 installation scripting_intro diff --git a/docs/source/using_yosys/more_scripting/index.rst b/docs/source/using_yosys/more_scripting/index.rst index 32aa8fc04..32879c0d4 100644 --- a/docs/source/using_yosys/more_scripting/index.rst +++ b/docs/source/using_yosys/more_scripting/index.rst @@ -1,7 +1,8 @@ More scripting -------------- -.. toctree:: +.. toctree:: + :maxdepth: 3 opt_passes selections diff --git a/docs/source/using_yosys/more_scripting/opt_passes.rst b/docs/source/using_yosys/more_scripting/opt_passes.rst index 3fd742560..15f2e20af 100644 --- a/docs/source/using_yosys/more_scripting/opt_passes.rst +++ b/docs/source/using_yosys/more_scripting/opt_passes.rst @@ -63,7 +63,7 @@ can also optimize cells with some constant inputs. 1 :math:`b` :math:`b` ========= ========= =========== -.. How to format table? +.. todo:: How to format table? :numref:`Table %s ` shows the replacement rules used for optimizing an ``$_AND_`` gate. The first three rules implement the obvious const @@ -96,9 +96,11 @@ This pass optimizes trees of multiplexer cells by analyzing the select inputs. Consider the following simple example: .. code:: verilog - :number-lines: - module uut(a, y); input a; output [1:0] y = a ? (a ? 1 : 2) : 3; endmodule + module uut(a, y); + input a; + output [1:0] y = a ? (a ? 1 : 2) : 3; + endmodule The output can never be 2, as this would require ``a`` to be 1 for the outer multiplexer and 0 for the inner multiplexer. The :cmd:ref:`opt_muxtree` pass @@ -123,8 +125,10 @@ Lastly this pass consolidates trees of ``$reduce_and`` cells and trees of These three simple optimizations are performed in a loop until a stable result is produced. -The :cmd:ref:`opt_rmdff` pass -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +The ``opt_rmdff`` pass +~~~~~~~~~~~~~~~~~~~~~~ + +.. todo:: The ``opt_rmdff`` pass doesn't exist anymore? This pass identifies single-bit d-type flip-flops (``$_DFF_``, ``$dff``, and ``$adff`` cells) with a constant data input and replaces them with a constant diff --git a/docs/source/yosys_internals/flow/index.rst b/docs/source/yosys_internals/flow/index.rst index 868aa08fe..3d05ea0bf 100644 --- a/docs/source/yosys_internals/flow/index.rst +++ b/docs/source/yosys_internals/flow/index.rst @@ -12,7 +12,7 @@ This scripts contain three types of commands: available: Verilog, BLIF, EDIF, SPICE, BTOR, . . .). .. toctree:: - :maxdepth: 2 + :maxdepth: 3 overview control_and_data diff --git a/docs/source/yosys_internals/flow/verilog_frontend.rst b/docs/source/yosys_internals/flow/verilog_frontend.rst index fbb82b416..2c8af3ad3 100644 --- a/docs/source/yosys_internals/flow/verilog_frontend.rst +++ b/docs/source/yosys_internals/flow/verilog_frontend.rst @@ -409,7 +409,9 @@ multiplexers. In more complex examples (e.g. asynchronous resets) the part of the ``RTLIL::CaseRule``/``RTLIL::SwitchRule`` tree that describes the asynchronous reset must first be transformed to the correct ``RTLIL::SyncRule`` objects. This -is done by the :cmd:ref:`proc_adff` pass. +is done by the ``proc_adff`` pass. + +.. todo:: The ``proc_adff`` pass doesn't exist anymore? The ProcessGenerator algorithm ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ diff --git a/docs/source/yosys_internals/formats/index.rst b/docs/source/yosys_internals/formats/index.rst index 2e6fba017..aa77d1ea6 100644 --- a/docs/source/yosys_internals/formats/index.rst +++ b/docs/source/yosys_internals/formats/index.rst @@ -2,7 +2,7 @@ Internal formats ================ .. toctree:: - :maxdepth: 2 + :maxdepth: 3 overview rtlil_rep diff --git a/docs/source/yosys_internals/formats/rtlil_rep.rst b/docs/source/yosys_internals/formats/rtlil_rep.rst index 904f80682..fa356e785 100644 --- a/docs/source/yosys_internals/formats/rtlil_rep.rst +++ b/docs/source/yosys_internals/formats/rtlil_rep.rst @@ -78,9 +78,9 @@ This has three advantages: - Second, the information about which identifiers were originally provided by the user is always available which can help guide some optimizations. For - example the :cmd:ref:`opt_rmunused` tries to preserve signals with a - user-provided name but doesn't hesitate to delete signals that have - auto-generated names when they just duplicate other signals. + example the ``opt_rmunused`` tries to preserve signals with a user-provided + name but doesn't hesitate to delete signals that have auto-generated names + when they just duplicate other signals. - Third, the delicate job of finding suitable auto-generated public visible names is deferred to one central location. Internally auto-generated names diff --git a/docs/source/yosys_internals/index.rst b/docs/source/yosys_internals/index.rst index c8b55cb8d..3389d88a0 100644 --- a/docs/source/yosys_internals/index.rst +++ b/docs/source/yosys_internals/index.rst @@ -23,7 +23,7 @@ wide range of real-world designs, including the `OpenRISC 1200 CPU`_, the .. _k68 CPU: http://opencores.org/projects/k68 -As of this writing a Yosys VHDL frontend is in development. +As of this writing, a Yosys VHDL frontend is in development. Yosys is written in C++ (using some features from the new C++11 standard). This chapter describes some of the fundamental Yosys data structures. For the sake of @@ -31,11 +31,10 @@ simplicity the C++ type names used in the Yosys implementation are used in this chapter, even though the chapter only explains the conceptual idea behind it and can be used as reference to implement a similar system in any language. -.. toctree:: +.. toctree:: + :maxdepth: 3 flow/index formats/index techmap extensions - -.. todo:: copypaste diff --git a/docs/util/cmdref.py b/docs/util/cmdref.py index 795a3e8ff..ec146e231 100644 --- a/docs/util/cmdref.py +++ b/docs/util/cmdref.py @@ -227,7 +227,7 @@ class CommandDomain(Domain): return make_refnode(builder,fromdocname,todocname, targ, contnode, title) else: - print("Awww, found nothing") + print(f"Missing ref for {target} in {fromdocname} ") return None def setup(app):