riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Add mux_map.v for wide mux

This commit is contained in:
Eddie Hung 2019-06-04 09:51:47 -07:00
parent 9b9bd4e19f
commit e260150321
4 changed files with 82 additions and 30 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
techlibs/xilinx/Makefile.inc
View File

@ -30,6 +30,7 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/mux_map.v))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc.box)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc.box))
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc.lut)) $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc.lut))

35
techlibs/xilinx/cells_map.v
View File

@ -2,6 +2,7 @@
* yosys -- Yosys Open SYnthesis Suite * yosys -- Yosys Open SYnthesis Suite
* *
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at> * Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* 2019 Eddie Hung <eddie@fpgeh.com>
* *
* Permission to use, copy, modify, and/or distribute this software for any * Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above * purpose with or without fee is hereby granted, provided that the above
@ -152,7 +153,7 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
endgenerate endgenerate
endmodule endmodule
module \$shiftx (A, B, Y); module \$__XILINX_MUX_ (A, B, Y);
parameter A_SIGNED = 0; parameter A_SIGNED = 0;
parameter B_SIGNED = 0; parameter B_SIGNED = 0;
parameter A_WIDTH = 1; parameter A_WIDTH = 1;
@ -184,18 +185,10 @@ module \$shiftx (A, B, Y);
generate generate
genvar i, j; genvar i, j;
// TODO: Check if this opt still necessary
if (B_SIGNED) begin
if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0)
// Optimisation to remove B_SIGNED if sign bit of B is constant-0
\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y));
else
wire _TECHMAP_FAIL_ = 1;
end
// Bit-blast // Bit-blast
else if (Y_WIDTH > 1) begin if (Y_WIDTH > 1) begin
for (i = 0; i < Y_WIDTH; i++) for (i = 0; i < Y_WIDTH; i++)
\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i])); \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH-Y_WIDTH+1), .B_WIDTH(B_WIDTH), .Y_WIDTH(1'd1)) bitblast (.A(A[A_WIDTH-Y_WIDTH+i:i]), .B(B), .Y(Y[i]));
end end
// If the LSB of B is constant zero (and Y_WIDTH is 1) then // If the LSB of B is constant zero (and Y_WIDTH is 1) then
// we can optimise by removing every other entry from A // we can optimise by removing every other entry from A
@ -204,24 +197,24 @@ module \$shiftx (A, B, Y);
wire [(A_WIDTH+1)/2-1:0] A_i; wire [(A_WIDTH+1)/2-1:0] A_i;
for (i = 0; i < (A_WIDTH+1)/2; i++) for (i = 0; i < (A_WIDTH+1)/2; i++)
assign A_i[i] = A[i*2]; assign A_i[i] = A[i*2];
\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y)); \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH((A_WIDTH+1'd1)/2'd2), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A_i), .B(B[B_WIDTH-1:1]), .Y(Y));
end end
// Trim off any leading 1'bx -es in A, and resize B accordingly // Trim off any leading 1'bx -es in A, and resize B accordingly
else if (num_leading_X_in_A > 0) begin else if (num_leading_X_in_A > 0) begin
localparam A_WIDTH_new = A_WIDTH - num_leading_X_in_A; localparam A_WIDTH_new = A_WIDTH - num_leading_X_in_A;
localparam B_WIDTH_new = $clog2(A_WIDTH_new); localparam B_WIDTH_new = $clog2(A_WIDTH_new);
\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH_new), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B[B_WIDTH_new-1:0]), .Y(Y)); \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH_new), .B_WIDTH(B_WIDTH_new), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A[A_WIDTH_new-1:0]), .B(B[B_WIDTH_new-1:0]), .Y(Y));
end end
else if (B_WIDTH < 3 || A_WIDTH <= 4) begin else if (B_WIDTH < 3 || A_WIDTH <= 4) begin
wire _TECHMAP_FAIL_ = 1; \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
end end
else if (B_WIDTH == 3) begin else if (B_WIDTH == 3) begin
localparam a_width0 = 2 ** 2; localparam a_width0 = 2 ** 2;
localparam a_widthN = A_WIDTH - a_width0; localparam a_widthN = A_WIDTH - a_width0;
wire T0, T1; wire T0, T1;
\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[a_width0-1:0]), .B(B[2-1:0]), .Y(T0)); \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_mux (.A(A[a_width0-1:0]), .B(B[2-1:0]), .Y(T0));
if (a_widthN > 1) if (a_widthN > 1)
\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1)); \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_mux_last (.A(A[A_WIDTH-1:a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T1));
else else
assign T1 = A[A_WIDTH-1]; assign T1 = A[A_WIDTH-1];
MUXF7 fpga_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y)); MUXF7 fpga_mux (.I0(T0), .I1(T1), .S(B[B_WIDTH-1]), .O(Y));
@ -234,10 +227,10 @@ module \$shiftx (A, B, Y);
wire T0, T1; wire T0, T1;
for (i = 0; i < 4; i++) for (i = 0; i < 4; i++)
if (i < num_mux8) if (i < num_mux8)
\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]), .Y(T[i])); \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(2), .Y_WIDTH(Y_WIDTH)) fpga_mux (.A(A[i*a_width0+:a_width0]), .B(B[2-1:0]), .Y(T[i]));
else if (i == num_mux8 && a_widthN > 0) begin else if (i == num_mux8 && a_widthN > 0) begin
if (a_widthN > 1) if (a_widthN > 1)
\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); \$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
else else
assign T[i] = A[A_WIDTH-1]; assign T[i] = A[A_WIDTH-1];
end end
@ -254,16 +247,16 @@ module \$shiftx (A, B, Y);
wire [(2**(B_WIDTH-4))-1:0] T; wire [(2**(B_WIDTH-4))-1:0] T;
for (i = 0; i < 2 ** (B_WIDTH-4); i++) for (i = 0; i < 2 ** (B_WIDTH-4); i++)
if (i < num_mux16) if (i < num_mux16)
\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i])); \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_width0), .B_WIDTH(4), .Y_WIDTH(Y_WIDTH)) fpga_mux (.A(A[i*a_width0+:a_width0]), .B(B[4-1:0]), .Y(T[i]));
else if (i == num_mux16 && a_widthN > 0) begin else if (i == num_mux16 && a_widthN > 0) begin
if (a_widthN > 1) if (a_widthN > 1)
\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_shiftx_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i])); \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(a_widthN), .B_WIDTH($clog2(a_widthN)), .Y_WIDTH(Y_WIDTH)) fpga_mux_last (.A(A[A_WIDTH-1:i*a_width0]), .B(B[$clog2(a_widthN)-1:0]), .Y(T[i]));
else else
assign T[i] = A[A_WIDTH-1]; assign T[i] = A[A_WIDTH-1];
end end
else else
assign T[i] = 1'bx; assign T[i] = 1'bx;
\$shiftx #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) fpga_shiftx (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y)); \$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(2**(B_WIDTH-4)), .B_WIDTH(B_WIDTH-4), .Y_WIDTH(Y_WIDTH)) fpga_mux (.A(T), .B(B[B_WIDTH-1:4]), .Y(Y));
end end
endgenerate endgenerate
endmodule endmodule

52
techlibs/xilinx/mux_map.v Normal file
View File

@ -0,0 +1,52 @@
/*
* yosys -- Yosys Open SYnthesis Suite
*
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
* 2019 Eddie Hung <eddie@fpgeh.com>
*
* Permission to use, copy, modify, and/or distribute this software for any
* purpose with or without fee is hereby granted, provided that the above
* copyright notice and this permission notice appear in all copies.
*
* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
*
*/
module \$shiftx (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 1;
parameter B_WIDTH = 1;
parameter Y_WIDTH = 1;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
parameter [B_WIDTH-1:0] _TECHMAP_CONSTMSK_B_ = 0;
parameter [B_WIDTH-1:0] _TECHMAP_CONSTVAL_B_ = 0;
generate
genvar i, j;
// TODO: Check if this opt still necessary
if (B_SIGNED) begin
if (_TECHMAP_CONSTMSK_B_[B_WIDTH-1] && _TECHMAP_CONSTVAL_B_[B_WIDTH-1] == 1'b0)
// Optimisation to remove B_SIGNED if sign bit of B is constant-0
\$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(0), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH-1'd1), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B[B_WIDTH-2:0]), .Y(Y));
else
wire _TECHMAP_FAIL_ = 1;
end
else if (B_WIDTH < 3 || A_WIDTH <= 4) begin
wire _TECHMAP_FAIL_ = 1;
end
else begin
\$__XILINX_MUX_ #(.A_SIGNED(A_SIGNED), .B_SIGNED(B_SIGNED), .A_WIDTH(A_WIDTH), .B_WIDTH(B_WIDTH), .Y_WIDTH(Y_WIDTH)) _TECHMAP_REPLACE_ (.A(A), .B(B), .Y(Y));
end
endgenerate
endmodule

24
techlibs/xilinx/synth_xilinx.cc
View File

@ -267,15 +267,21 @@ struct SynthXilinxPass : public ScriptPass
run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')"); run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
} }
if (vpr && !nocarry && !help_mode) std::string techmap_files = " -map +/techmap.v";
run("techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY"); if (help_mode)
else if (abc == "abc9" && !nocarry && !help_mode) techmap_files += " [-map +/xilinx/mux_map.v]";
run("techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _CLB_CARRY"); else if (!nomux)
else if (!nocarry || help_mode) techmap_files += " -map +/xilinx/mux_map.v";
run("techmap -map +/techmap.v -map +/xilinx/arith_map.v", "(skip if '-nocarry')"); if (help_mode)
else techmap_files += " [-map +/xilinx/arith_map.v]";
run("techmap -map +/techmap.v"); else if (!nocarry) {
techmap_files += " -map +/xilinx/arith_map.v";
if (vpr)
techmap_files += " -D _EXPLICIT_CARRY";
else if (abc == "abc9")
techmap_files += " -D _CLB_CARRY";
}
run("techmap " + techmap_files);
run("opt -fast"); run("opt -fast");
} }