From e22fee6cdd905535c50c9b6d96a89e994944ea2c Mon Sep 17 00:00:00 2001 From: Eddie Hung Date: Thu, 13 Feb 2020 11:15:59 -0800 Subject: [PATCH] abc9_ops: ignore (* abc9_flop *) if not '-dff' --- backends/aiger/xaiger.cc | 86 +++++++++++++----------- passes/techmap/abc9.cc | 8 +-- passes/techmap/abc9_ops.cc | 128 ++++++++++++++++++------------------ techlibs/xilinx/cells_sim.v | 8 ++- 4 files changed, 120 insertions(+), 110 deletions(-) diff --git a/backends/aiger/xaiger.cc b/backends/aiger/xaiger.cc index c996b0776..16d48a932 100644 --- a/backends/aiger/xaiger.cc +++ b/backends/aiger/xaiger.cc @@ -186,7 +186,6 @@ struct XAigerWriter dict>> arrivals_cache; for (auto cell : module->cells()) { - RTLIL::Module* inst_module = module->design->module(cell->type); if (!cell->has_keep_attr()) { if (cell->type == "$_NOT_") { @@ -229,9 +228,16 @@ struct XAigerWriter if (cell->type.in("$specify2", "$specify3", "$specrule")) continue; + } - if (inst_module) { - bool abc9_flop = false; + RTLIL::Module* inst_module = module->design->module(cell->type); + if (inst_module) { + IdString derived_type = inst_module->derive(module->design, cell->parameters); + inst_module = module->design->module(derived_type); + log_assert(inst_module); + + bool abc9_flop = false; + if (!cell->has_keep_attr()) { auto it = cell->attributes.find("\\abc9_box_seq"); if (it != cell->attributes.end()) { int abc9_box_seq = it->second.as_int(); @@ -244,50 +250,50 @@ struct XAigerWriter if (!abc9_flop) continue; } + } - auto &cell_arrivals = arrivals_cache[cell->type]; - for (const auto &conn : cell->connections()) { - auto port_wire = inst_module->wire(conn.first); - if (!port_wire->port_output) + auto &cell_arrivals = arrivals_cache[derived_type]; + for (const auto &conn : cell->connections()) { + auto port_wire = inst_module->wire(conn.first); + if (!port_wire->port_output) + continue; + + auto r = cell_arrivals.insert(conn.first); + auto &arrivals = r.first->second; + if (r.second) { + auto it = port_wire->attributes.find("\\abc9_arrival"); + if (it == port_wire->attributes.end()) continue; - - auto r = cell_arrivals.insert(conn.first); - auto &arrivals = r.first->second; - if (r.second) { - auto it = port_wire->attributes.find("\\abc9_arrival"); - if (it == port_wire->attributes.end()) - continue; - if (it->second.flags == 0) - arrivals.emplace_back(it->second.as_int()); - else - for (const auto &tok : split_tokens(it->second.decode_string())) - arrivals.push_back(atoi(tok.c_str())); - } - - if (arrivals.empty()) - continue; - - if (GetSize(arrivals) > 1 && GetSize(arrivals) != GetSize(port_wire)) - log_error("%s.%s is %d bits wide but abc9_arrival = %s has %d value(s)!\n", log_id(cell->type), log_id(conn.first), - GetSize(port_wire), log_signal(it->second), GetSize(arrivals)); - - auto jt = arrivals.begin(); -#ifndef NDEBUG - if (ys_debug(1)) { - static std::set> seen; - if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_arrival = %d\n", log_id(cell->type), log_id(conn.first), *jt); - } -#endif - for (auto bit : sigmap(conn.second)) { - arrival_times[bit] = *jt; - if (arrivals.size() > 1) - jt++; + if (it->second.flags == 0) + arrivals.emplace_back(it->second.as_int()); + else { + for (const auto &tok : split_tokens(it->second.decode_string())) + arrivals.push_back(atoi(tok.c_str())); + if (GetSize(arrivals) > 1 && GetSize(arrivals) != GetSize(port_wire)) + log_error("%s.%s is %d bits wide but abc9_arrival = '%s' has %d value(s)!\n", log_id(cell->type), log_id(conn.first), + GetSize(port_wire), log_signal(it->second), GetSize(arrivals)); } } - if (abc9_flop) + if (arrivals.empty()) continue; + + auto jt = arrivals.begin(); +#ifndef NDEBUG + if (ys_debug(1)) { + static std::set> seen; + if (seen.emplace(derived_type, conn.first).second) log("%s.%s abc9_arrival = %d\n", log_id(cell->type), log_id(conn.first), *jt); + } +#endif + for (auto bit : sigmap(conn.second)) { + arrival_times[bit] = *jt; + if (arrivals.size() > 1) + jt++; + } } + + if (abc9_flop) + continue; } bool cell_known = inst_module || cell->known(); diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc index fc82f0e5f..5e650230d 100644 --- a/passes/techmap/abc9.cc +++ b/passes/techmap/abc9.cc @@ -192,7 +192,7 @@ struct Abc9Pass : public ScriptPass cleanup = true; lut_mode = false; maxlut = 0; - box_file = "(null)"; + box_file = ""; } void execute(std::vector args, RTLIL::Design *design) YS_OVERRIDE @@ -286,9 +286,9 @@ struct Abc9Pass : public ScriptPass else if (!lut_mode) run(stringf("abc9_ops -prep_lut %d", maxlut)); if (help_mode) - run("abc9_ops -prep_box [<-box>|(null)]"); - else - run(stringf("abc9_ops -prep_box %s", box_file.c_str())); + run("abc9_ops -prep_box [-dff]", "(skip if -box)"); + else if (box_file.empty()) + run(stringf("abc9_ops -prep_box %s", dff_mode ? "-dff" : "")); run("select -set abc9_holes A:abc9_holes"); run("flatten -wb @abc9_holes"); run("techmap @abc9_holes"); diff --git a/passes/techmap/abc9_ops.cc b/passes/techmap/abc9_ops.cc index e1ab70f11..f3d3381cd 100644 --- a/passes/techmap/abc9_ops.cc +++ b/passes/techmap/abc9_ops.cc @@ -378,7 +378,7 @@ void prep_xaiger(RTLIL::Module *module, bool dff) } } -void prep_delays(RTLIL::Design *design) +void prep_delays(RTLIL::Design *design, bool dff_mode) { // Derive and collect all Yosys blackbox modules that are not combinatorial abc9 boxes // (e.g. DSPs, RAMs, etc.) nor abc9 flops and collect all such instantiations @@ -407,7 +407,7 @@ void prep_delays(RTLIL::Design *design) log_assert(inst_module); blackboxes.insert(inst_module); - if (inst_module->get_bool_attribute(ID(abc9_flop))) { + if (dff_mode && inst_module->get_bool_attribute(ID(abc9_flop))) { flops.insert(inst_module); continue; // do not add $__ABC9_DELAY boxes to flops // as delays will be captured in the flop box @@ -474,10 +474,8 @@ void prep_delays(RTLIL::Design *design) continue; ports.clear(); - for (const auto &i : arrivals) { - log_dump(i.first, i.first.wire->name); + for (const auto &i : arrivals) ports.insert(i.first.wire); - } for (auto wire : ports) { log_assert(wire->port_output); ss.str(""); @@ -537,7 +535,7 @@ void prep_delays(RTLIL::Design *design) inst_module = design->module(derived_type); log_assert(inst_module); - auto &cell_requireds = requireds_cache[cell->type]; + auto &cell_requireds = requireds_cache[derived_type]; for (auto &conn : cell->connections_) { auto port_wire = inst_module->wire(conn.first); if (!port_wire->port_input) @@ -569,7 +567,7 @@ void prep_delays(RTLIL::Design *design) #ifndef NDEBUG if (ys_debug(1)) { static std::set> seen; - if (seen.emplace(cell->type, conn.first).second) log("%s.%s abc9_required = %d\n", log_id(cell->type), log_id(conn.first), requireds[i]); + if (seen.emplace(derived_type, conn.first).second) log("%s.%s abc9_required = %d\n", log_id(cell->type), log_id(conn.first), requireds[i]); } #endif auto box = module->addCell(NEW_ID, ID($__ABC9_DELAY)); @@ -652,64 +650,66 @@ void write_lut(RTLIL::Module *module, const std::string &dst) { ofs.close(); } -void prep_box(RTLIL::Design *design) +void prep_box(RTLIL::Design *design, bool dff_mode) { std::stringstream ss; int abc9_box_id = 1; dict> box_ports; for (auto module : design->modules()) { - if (module->get_bool_attribute(ID(abc9_flop))) { - int num_inputs = 0, num_outputs = 0; - for (auto port_name : module->ports) { - auto wire = module->wire(port_name); - log_assert(GetSize(wire) == 1); - if (wire->port_input) num_inputs++; - if (wire->port_output) num_outputs++; + auto abc9_flop = module->get_bool_attribute(ID(abc9_flop)); + if (abc9_flop) { + if (dff_mode) { + int num_inputs = 0, num_outputs = 0; + for (auto port_name : module->ports) { + auto wire = module->wire(port_name); + log_assert(GetSize(wire) == 1); + if (wire->port_input) num_inputs++; + if (wire->port_output) num_outputs++; + } + log_assert(num_outputs == 1); + + auto r = module->attributes.insert(ID(abc9_box_id)); + if (r.second) + r.first->second = abc9_box_id++; + + ss << log_id(module) << " " << r.first->second.as_int(); + ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0"); + ss << " " << num_inputs+1 << " " << num_outputs << std::endl; + + ss << "#"; + bool first = true; + for (auto port_name : module->ports) { + auto wire = module->wire(port_name); + if (!wire->port_input) + continue; + if (first) + first = false; + else + ss << " "; + ss << log_id(wire); + } + ss << " abc9_ff.Q" << std::endl; + + first = true; + for (auto port_name : module->ports) { + auto wire = module->wire(port_name); + if (!wire->port_input) + continue; + if (first) + first = false; + else + ss << " "; + ss << wire->attributes.at("\\abc9_required", 0).as_int(); + } + // Last input is 'abc9_ff.Q' + ss << " 0" << std::endl << std::endl; + continue; } - log_assert(num_outputs == 1); - - auto r = module->attributes.insert(ID(abc9_box_id)); - if (r.second) - r.first->second = abc9_box_id++; - - ss << log_id(module) << " " << r.first->second.as_int(); - ss << " " << (module->get_bool_attribute(ID::whitebox) ? "1" : "0"); - ss << " " << num_inputs+1 << " " << num_outputs << std::endl; - - ss << "#"; - bool first = true; - for (auto port_name : module->ports) { - auto wire = module->wire(port_name); - if (!wire->port_input) - continue; - if (first) - first = false; - else - ss << " "; - ss << log_id(wire); - } - ss << " abc9_ff.Q" << std::endl; - - first = true; - for (auto port_name : module->ports) { - auto wire = module->wire(port_name); - if (!wire->port_input) - continue; - if (first) - first = false; - else - ss << " "; - ss << wire->attributes.at("\\abc9_required", 0).as_int(); - } - // Last input is 'abc9_ff.Q' - ss << " 0" << std::endl << std::endl; - continue; } - - auto it = module->attributes.find(ID(abc9_box)); - if (it == module->attributes.end()) - continue; - module->attributes.erase(it); + else { + if (!module->attributes.erase(ID(abc9_box))) + continue; + } log_assert(!module->attributes.count(ID(abc9_box_id))); dict, std::string> table; @@ -1241,8 +1241,8 @@ struct Abc9OpsPass : public Pass { log(" whiteboxes.\n"); log("\n"); log(" -dff\n"); - log(" consider flop cells (those instantiating modules marked with (* abc9_flop *)\n"); - log(" during -prep_xaiger.\n"); + log(" consider flop cells (those instantiating modules marked with (* abc9_flop *))\n"); + log(" during -prep_{delays,xaiger,box}.\n"); log("\n"); log(" -prep_dff\n"); log(" compute the clock domain and initial value of each flop in the design.\n"); @@ -1345,17 +1345,17 @@ struct Abc9OpsPass : public Pass { if (!(check_mode || mark_scc_mode || prep_delays_mode || prep_xaiger_mode || prep_dff_mode || prep_lut_mode || prep_box_mode || !write_lut_dst.empty() || !write_box_dst.empty() || reintegrate_mode)) log_cmd_error("At least one of -check, -mark_scc, -prep_{delays,xaiger,dff,lut,box}, -write_{lut,box}, -reintegrate must be specified.\n"); - if (dff_mode && !prep_xaiger_mode) - log_cmd_error("'-dff' option is only relevant for -prep_xaiger.\n"); + if (dff_mode && !prep_delays_mode && !prep_xaiger_mode && !prep_box_mode) + log_cmd_error("'-dff' option is only relevant for -prep_{delay,xaiger,box}.\n"); if (check_mode) check(design); if (prep_delays_mode) - prep_delays(design); + prep_delays(design, dff_mode); if (prep_lut_mode) prep_lut(design, maxlut); if (prep_box_mode) - prep_box(design); + prep_box(design, dff_mode); for (auto mod : design->selected_modules()) { if (mod->get_bool_attribute("\\abc9_holes")) diff --git a/techlibs/xilinx/cells_sim.v b/techlibs/xilinx/cells_sim.v index 0be53ef9e..4b094fb5b 100644 --- a/techlibs/xilinx/cells_sim.v +++ b/techlibs/xilinx/cells_sim.v @@ -492,8 +492,8 @@ module FDRE ( endgenerate specify // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L249 - //$setup(D , posedge C &&& CE &&& !IS_C_INVERTED , -46); // Negative times not currently supported - //$setup(D , negedge C &&& CE &&& IS_C_INVERTED , -46); // Negative times not currently supported + //$setup(D , posedge C &&& CE && !IS_C_INVERTED , -46); // Negative times not currently supported + //$setup(D , negedge C &&& CE && IS_C_INVERTED , -46); // Negative times not currently supported // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 $setup(CE, posedge C &&& !IS_C_INVERTED, 109); $setup(CE, negedge C &&& IS_C_INVERTED, 109); @@ -665,6 +665,7 @@ module FDCE ( // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 $setup(CE , posedge C &&& !IS_C_INVERTED, 109); $setup(CE , negedge C &&& IS_C_INVERTED, 109); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 $setup(CLR, posedge C &&& !IS_C_INVERTED, 404); $setup(CLR, negedge C &&& IS_C_INVERTED, 404); // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270 @@ -692,6 +693,7 @@ module FDCE_1 ( //$setup(D , negedge C &&& CE, -46); // Negative times not currently supported // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 $setup(CE , negedge C, 109); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 $setup(CLR, negedge C, 404); // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270 //(posedge CLR => (Q : 1'b0)) = 764; // Captured by $__ABC9_ASYNC0 @@ -730,6 +732,7 @@ module FDPE ( // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 $setup(CE , posedge C &&& !IS_C_INVERTED, 109); $setup(CE , negedge C &&& IS_C_INVERTED, 109); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 $setup(PRE, posedge C &&& !IS_C_INVERTED, 404); $setup(PRE, negedge C &&& IS_C_INVERTED, 404); // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270 @@ -757,6 +760,7 @@ module FDPE_1 ( //$setup(D , negedge C &&& CE, -46); // Negative times not currently supported // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L248 $setup(CE , negedge C, 109); + // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L274 $setup(PRE, negedge C, 404); // https://github.com/SymbiFlow/prjxray-db/blob/23c8b0851f979f0799318eaca90174413a46b257/artix7/timings/slicel.sdf#L270 //if (!IS_PRE_INVERTED) (posedge PRE => (Q : 1'b1)) = 764; // Captured by $__ABC9_ASYNC1