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Merge branch 'master' into firrtl+modules+shiftfixes

This commit is contained in:
Jim Lawson 2018-08-27 12:13:04 -07:00
parent 380c6f0e97 604b5d4e20
commit e217c6c52f
12 changed files with 92 additions and 39 deletions
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4
.gitignore vendored
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@ -2,6 +2,8 @@
*.d *.d
.*.swp .*.swp
*.gch *.gch
*.gcda
*.gcno
/.cproject /.cproject
/.project /.project
/.settings /.settings
@ -10,6 +12,8 @@
/qtcreator.config /qtcreator.config
/qtcreator.creator /qtcreator.creator
/qtcreator.creator.user /qtcreator.creator.user
/coverage.info
/coverage_html
/Makefile.conf /Makefile.conf
/abc /abc
/viz.js /viz.js

21
Makefile
View File

@ -19,6 +19,7 @@ ENABLE_LIBYOSYS := 0
ENABLE_PROTOBUF := 0 ENABLE_PROTOBUF := 0
# other configuration flags # other configuration flags
ENABLE_GCOV := 0
ENABLE_GPROF := 0 ENABLE_GPROF := 0
ENABLE_DEBUG := 0 ENABLE_DEBUG := 0
ENABLE_NDEBUG := 0 ENABLE_NDEBUG := 0
@ -158,7 +159,7 @@ ABCMKARGS += ARCHFLAGS="-DABC_USE_STDINT_H"
else ifeq ($(CONFIG),gcc-static) else ifeq ($(CONFIG),gcc-static)
LD = $(CXX) LD = $(CXX)
LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -s LDFLAGS := $(filter-out -rdynamic,$(LDFLAGS)) -static
LDLIBS := $(filter-out -lrt,$(LDLIBS)) LDLIBS := $(filter-out -lrt,$(LDLIBS))
CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS)) CXXFLAGS := $(filter-out -fPIC,$(CXXFLAGS))
CXXFLAGS += -std=c++11 -Os CXXFLAGS += -std=c++11 -Os
@ -312,6 +313,11 @@ endif
endif endif
endif endif
ifeq ($(ENABLE_GCOV),1)
CXXFLAGS += --coverage
LDFLAGS += --coverage
endif
ifeq ($(ENABLE_GPROF),1) ifeq ($(ENABLE_GPROF),1)
CXXFLAGS += -pg CXXFLAGS += -pg
LDFLAGS += -pg LDFLAGS += -pg
@ -644,6 +650,12 @@ clean-abc:
mrproper: clean mrproper: clean
git clean -xdf git clean -xdf
coverage:
./yosys -qp 'help; help -all'
rm -rf coverage.info coverage_html
lcov --capture -d . --no-external -o coverage.info
genhtml coverage.info --output-directory coverage_html
qtcreator: qtcreator:
{ for file in $(basename $(OBJS)); do \ { for file in $(basename $(OBJS)); do \
for prefix in cc y l; do if [ -f $${file}.$${prefix} ]; then echo $$file.$${prefix}; fi; done \ for prefix in cc y l; do if [ -f $${file}.$${prefix} ]; then echo $$file.$${prefix}; fi; done \
@ -709,6 +721,11 @@ config-msys2: clean
config-msys2-64: clean config-msys2-64: clean
echo 'CONFIG := msys2-64' > Makefile.conf echo 'CONFIG := msys2-64' > Makefile.conf
config-gcov: clean
echo 'CONFIG := gcc' > Makefile.conf
echo 'ENABLE_GCOV := 1' >> Makefile.conf
echo 'ENABLE_DEBUG := 1' >> Makefile.conf
config-gprof: clean config-gprof: clean
echo 'CONFIG := gcc' > Makefile.conf echo 'CONFIG := gcc' > Makefile.conf
echo 'ENABLE_GPROF := 1' >> Makefile.conf echo 'ENABLE_GPROF := 1' >> Makefile.conf
@ -729,6 +746,6 @@ echo-git-rev:
-include kernel/*.d -include kernel/*.d
-include techlibs/*/*.d -include techlibs/*/*.d
.PHONY: all top-all abc test install install-abc manual clean mrproper qtcreator .PHONY: all top-all abc test install install-abc manual clean mrproper qtcreator coverage vcxsrc mxebin
.PHONY: config-clean config-clang config-gcc config-gcc-static config-gcc-4.8 config-gprof config-sudo .PHONY: config-clean config-clang config-gcc config-gcc-static config-gcc-4.8 config-gprof config-sudo

15
frontends/ast/ast.cc
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@ -44,7 +44,7 @@ namespace AST {
// instanciate global variables (private API) // instanciate global variables (private API)
namespace AST_INTERNAL { namespace AST_INTERNAL {
bool flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit; bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire; bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
AstNode *current_ast, *current_ast_mod; AstNode *current_ast, *current_ast_mod;
std::map<std::string, AstNode*> current_scope; std::map<std::string, AstNode*> current_scope;
@ -267,10 +267,12 @@ void AstNode::dumpAst(FILE *f, std::string indent) const
std::string type_name = type2str(type); std::string type_name = type2str(type);
fprintf(f, "%s%s <%s:%d>", indent.c_str(), type_name.c_str(), filename.c_str(), linenum); fprintf(f, "%s%s <%s:%d>", indent.c_str(), type_name.c_str(), filename.c_str(), linenum);
if (id2ast) if (!flag_no_dump_ptr) {
fprintf(f, " [%p -> %p]", this, id2ast); if (id2ast)
else fprintf(f, " [%p -> %p]", this, id2ast);
fprintf(f, " [%p]", this); else
fprintf(f, " [%p]", this);
}
if (!str.empty()) if (!str.empty())
fprintf(f, " str='%s'", str.c_str()); fprintf(f, " str='%s'", str.c_str());
@ -1008,12 +1010,13 @@ static AstModule* process_module(AstNode *ast, bool defer)
} }
// create AstModule instances for all modules in the AST tree and add them to 'design' // create AstModule instances for all modules in the AST tree and add them to 'design'
void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil, void AST::process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog, bool dump_rtlil,
bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire) bool nolatches, bool nomeminit, bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire)
{ {
current_ast = ast; current_ast = ast;
flag_dump_ast1 = dump_ast1; flag_dump_ast1 = dump_ast1;
flag_dump_ast2 = dump_ast2; flag_dump_ast2 = dump_ast2;
flag_no_dump_ptr = no_dump_ptr;
flag_dump_vlog = dump_vlog; flag_dump_vlog = dump_vlog;
flag_dump_rtlil = dump_rtlil; flag_dump_rtlil = dump_rtlil;
flag_nolatches = nolatches; flag_nolatches = nolatches;

4
frontends/ast/ast.h
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@ -274,7 +274,7 @@ namespace AST
}; };
// process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code // process an AST tree (ast must point to an AST_DESIGN node) and generate RTLIL code
void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit, void process(RTLIL::Design *design, AstNode *ast, bool dump_ast1, bool dump_ast2, bool no_dump_ptr, bool dump_vlog, bool dump_rtlil, bool nolatches, bool nomeminit,
bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire); bool nomem2reg, bool mem2reg, bool lib, bool noopt, bool icells, bool nooverwrite, bool overwrite, bool defer, bool autowire);
// parametric modules are supported directly by the AST library // parametric modules are supported directly by the AST library
@ -305,7 +305,7 @@ namespace AST
namespace AST_INTERNAL namespace AST_INTERNAL
{ {
// internal state variables // internal state variables
extern bool flag_dump_ast1, flag_dump_ast2, flag_dump_rtlil, flag_nolatches, flag_nomeminit; extern bool flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_rtlil, flag_nolatches, flag_nomeminit;
extern bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire; extern bool flag_nomem2reg, flag_mem2reg, flag_lib, flag_noopt, flag_icells, flag_autowire;
extern AST::AstNode *current_ast, *current_ast_mod; extern AST::AstNode *current_ast, *current_ast_mod;
extern std::map<std::string, AST::AstNode*> current_scope; extern std::map<std::string, AST::AstNode*> current_scope;

2
frontends/ilang/.gitignore vendored
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@ -1,4 +1,4 @@
ilang_lexer.cc ilang_lexer.cc
ilang_parser.output ilang_parser.output
ilang_parser.tab.cc ilang_parser.tab.cc
ilang_parser.tab.h ilang_parser.tab.hh

7
frontends/ilang/Makefile.inc
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@ -1,15 +1,14 @@
GENFILES += frontends/ilang/ilang_parser.tab.cc GENFILES += frontends/ilang/ilang_parser.tab.cc
GENFILES += frontends/ilang/ilang_parser.tab.h GENFILES += frontends/ilang/ilang_parser.tab.hh
GENFILES += frontends/ilang/ilang_parser.output GENFILES += frontends/ilang/ilang_parser.output
GENFILES += frontends/ilang/ilang_lexer.cc GENFILES += frontends/ilang/ilang_lexer.cc
frontends/ilang/ilang_parser.tab.cc: frontends/ilang/ilang_parser.y frontends/ilang/ilang_parser.tab.cc: frontends/ilang/ilang_parser.y
$(Q) mkdir -p $(dir $@) $(Q) mkdir -p $(dir $@)
$(P) $(BISON) -d -r all -b frontends/ilang/ilang_parser $< $(P) $(BISON) -o $@ -d -r all -b frontends/ilang/ilang_parser $<
$(Q) mv frontends/ilang/ilang_parser.tab.c frontends/ilang/ilang_parser.tab.cc
frontends/ilang/ilang_parser.tab.h: frontends/ilang/ilang_parser.tab.cc frontends/ilang/ilang_parser.tab.hh: frontends/ilang/ilang_parser.tab.cc
frontends/ilang/ilang_lexer.cc: frontends/ilang/ilang_lexer.l frontends/ilang/ilang_lexer.cc: frontends/ilang/ilang_lexer.l
$(Q) mkdir -p $(dir $@) $(Q) mkdir -p $(dir $@)

2
frontends/ilang/ilang_lexer.l
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@ -30,7 +30,7 @@
#endif #endif
#include "frontends/ilang/ilang_frontend.h" #include "frontends/ilang/ilang_frontend.h"
#include "ilang_parser.tab.h" #include "ilang_parser.tab.hh"
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE

2
frontends/verilog/.gitignore vendored
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@ -1,4 +1,4 @@
verilog_lexer.cc verilog_lexer.cc
verilog_parser.output verilog_parser.output
verilog_parser.tab.cc verilog_parser.tab.cc
verilog_parser.tab.h verilog_parser.tab.hh

7
frontends/verilog/Makefile.inc
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@ -1,15 +1,14 @@
GENFILES += frontends/verilog/verilog_parser.tab.cc GENFILES += frontends/verilog/verilog_parser.tab.cc
GENFILES += frontends/verilog/verilog_parser.tab.h GENFILES += frontends/verilog/verilog_parser.tab.hh
GENFILES += frontends/verilog/verilog_parser.output GENFILES += frontends/verilog/verilog_parser.output
GENFILES += frontends/verilog/verilog_lexer.cc GENFILES += frontends/verilog/verilog_lexer.cc
frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y frontends/verilog/verilog_parser.tab.cc: frontends/verilog/verilog_parser.y
$(Q) mkdir -p $(dir $@) $(Q) mkdir -p $(dir $@)
$(P) $(BISON) -d -r all -b frontends/verilog/verilog_parser $< $(P) $(BISON) -o $@ -d -r all -b frontends/verilog/verilog_parser $<
$(Q) mv frontends/verilog/verilog_parser.tab.c frontends/verilog/verilog_parser.tab.cc
frontends/verilog/verilog_parser.tab.h: frontends/verilog/verilog_parser.tab.cc frontends/verilog/verilog_parser.tab.hh: frontends/verilog/verilog_parser.tab.cc
frontends/verilog/verilog_lexer.cc: frontends/verilog/verilog_lexer.l frontends/verilog/verilog_lexer.cc: frontends/verilog/verilog_lexer.l
$(Q) mkdir -p $(dir $@) $(Q) mkdir -p $(dir $@)

10
frontends/verilog/verilog_frontend.cc
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@ -78,6 +78,9 @@ struct VerilogFrontend : public Frontend {
log(" -dump_ast2\n"); log(" -dump_ast2\n");
log(" dump abstract syntax tree (after simplification)\n"); log(" dump abstract syntax tree (after simplification)\n");
log("\n"); log("\n");
log(" -no_dump_ptr\n");
log(" do not include hex memory addresses in dump (easier to diff dumps)\n");
log("\n");
log(" -dump_vlog\n"); log(" -dump_vlog\n");
log(" dump ast as Verilog code (after simplification)\n"); log(" dump ast as Verilog code (after simplification)\n");
log("\n"); log("\n");
@ -184,6 +187,7 @@ struct VerilogFrontend : public Frontend {
{ {
bool flag_dump_ast1 = false; bool flag_dump_ast1 = false;
bool flag_dump_ast2 = false; bool flag_dump_ast2 = false;
bool flag_no_dump_ptr = false;
bool flag_dump_vlog = false; bool flag_dump_vlog = false;
bool flag_dump_rtlil = false; bool flag_dump_rtlil = false;
bool flag_nolatches = false; bool flag_nolatches = false;
@ -241,6 +245,10 @@ struct VerilogFrontend : public Frontend {
flag_dump_ast2 = true; flag_dump_ast2 = true;
continue; continue;
} }
if (arg == "-no_dump_ptr") {
flag_no_dump_ptr = true;
continue;
}
if (arg == "-dump_vlog") { if (arg == "-dump_vlog") {
flag_dump_vlog = true; flag_dump_vlog = true;
continue; continue;
@ -381,7 +389,7 @@ struct VerilogFrontend : public Frontend {
if (flag_nodpi) if (flag_nodpi)
error_on_dpi_function(current_ast); error_on_dpi_function(current_ast);
AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire); AST::process(design, current_ast, flag_dump_ast1, flag_dump_ast2, flag_no_dump_ptr, flag_dump_vlog, flag_dump_rtlil, flag_nolatches, flag_nomeminit, flag_nomem2reg, flag_mem2reg, lib_mode, flag_noopt, flag_icells, flag_nooverwrite, flag_overwrite, flag_defer, default_nettype_wire);
if (!flag_nopp) if (!flag_nopp)
delete lexin; delete lexin;

2
frontends/verilog/verilog_lexer.l
View File

@ -42,7 +42,7 @@
#include "kernel/log.h" #include "kernel/log.h"
#include "frontends/verilog/verilog_frontend.h" #include "frontends/verilog/verilog_frontend.h"
#include "frontends/ast/ast.h" #include "frontends/ast/ast.h"
#include "verilog_parser.tab.h" #include "verilog_parser.tab.hh"
USING_YOSYS_NAMESPACE USING_YOSYS_NAMESPACE
using namespace AST; using namespace AST;

55
frontends/verilog/verilog_parser.y
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@ -654,7 +654,7 @@ specify_item:
// | pulsestyle_declaration // | pulsestyle_declaration
// | showcancelled_declaration // | showcancelled_declaration
| path_declaration | path_declaration
// | system_timing_declaration | system_timing_declaration
; ;
specparam_declaration: specparam_declaration:
@ -682,22 +682,23 @@ showcancelled_declaration :
*/ */
path_declaration : path_declaration :
simple_path_declaration simple_path_declaration ';'
// | edge_sensitive_path_declaration // | edge_sensitive_path_declaration
// | state_dependent_path_declaration // | state_dependent_path_declaration
; ;
simple_path_declaration : simple_path_declaration :
parallel_path_description '=' path_delay_value ';' parallel_path_description '=' path_delay_value |
// | full_path_description '=' path_delay_value ';' full_path_description '=' path_delay_value
; ;
path_delay_value : path_delay_value :
//list_of_path_delay_expressions '(' path_delay_expression list_of_path_delay_extra_expressions ')'
'(' list_of_path_delay_expressions ')' | path_delay_expression
| path_delay_expression list_of_path_delay_extra_expressions
; ;
list_of_path_delay_expressions : list_of_path_delay_extra_expressions :
/* /*
t_path_delay_expression t_path_delay_expression
| trise_path_delay_expression ',' tfall_path_delay_expression | trise_path_delay_expression ',' tfall_path_delay_expression
@ -709,12 +710,11 @@ list_of_path_delay_expressions :
t0x_path_delay_expression ',' tx1_path_delay_expression ',' t1x_path_delay_expression ',' t0x_path_delay_expression ',' tx1_path_delay_expression ',' t1x_path_delay_expression ','
tx0_path_delay_expression ',' txz_path_delay_expression ',' tzx_path_delay_expression tx0_path_delay_expression ',' txz_path_delay_expression ',' tzx_path_delay_expression
*/ */
path_delay_expression ',' path_delay_expression
| path_delay_expression ',' path_delay_expression | ',' path_delay_expression ',' path_delay_expression
| path_delay_expression ',' path_delay_expression ',' path_delay_expression | ',' path_delay_expression ',' path_delay_expression ','
| path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
path_delay_expression ',' path_delay_expression ',' path_delay_expression path_delay_expression ',' path_delay_expression ',' path_delay_expression
| path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' | ',' path_delay_expression ',' path_delay_expression ','
path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ',' path_delay_expression ','
path_delay_expression ',' path_delay_expression ',' path_delay_expression path_delay_expression ',' path_delay_expression ',' path_delay_expression
@ -723,6 +723,22 @@ list_of_path_delay_expressions :
parallel_path_description : parallel_path_description :
'(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' ; '(' specify_input_terminal_descriptor opt_polarity_operator '=' '>' specify_output_terminal_descriptor ')' ;
full_path_description :
'(' list_of_path_inputs '*' '>' list_of_path_outputs ')' ;
// This was broken into 2 rules to solve shift/reduce conflicts
list_of_path_inputs :
specify_input_terminal_descriptor opt_polarity_operator |
specify_input_terminal_descriptor more_path_inputs opt_polarity_operator ;
more_path_inputs :
',' specify_input_terminal_descriptor |
more_path_inputs ',' specify_input_terminal_descriptor ;
list_of_path_outputs :
specify_output_terminal_descriptor |
list_of_path_outputs ',' specify_output_terminal_descriptor ;
opt_polarity_operator : opt_polarity_operator :
'+' '+'
| '-' | '-'
@ -736,10 +752,17 @@ specify_input_terminal_descriptor :
specify_output_terminal_descriptor : specify_output_terminal_descriptor :
TOK_ID ; TOK_ID ;
/*
system_timing_declaration : system_timing_declaration :
; TOK_ID '(' system_timing_args ')' ';' ;
*/
system_timing_arg :
TOK_POSEDGE TOK_ID |
TOK_NEGEDGE TOK_ID |
expr ;
system_timing_args :
system_timing_arg |
system_timing_args ',' system_timing_arg ;
/* /*
t_path_delay_expression : t_path_delay_expression :
@ -792,7 +815,7 @@ tzx_path_delay_expression :
*/ */
path_delay_expression : path_delay_expression :
constant_mintypmax_expression; constant_expression;
constant_mintypmax_expression : constant_mintypmax_expression :
constant_expression constant_expression