check: Extend testing

This commit is contained in:
Martin Povišer 2024-02-12 12:32:15 +01:00
parent b6112b3551
commit e1e77a7fa9
3 changed files with 69 additions and 1 deletions

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@ -1,5 +1,5 @@
design -reset design -reset
read_verilog <<EOF read -vlog2k <<EOF
module top(input clk, input a, input b, output [9:0] x); module top(input clk, input a, input b, output [9:0] x);
wire [9:0] ripple; wire [9:0] ripple;
reg [9:0] prev_ripple = 9'b0; reg [9:0] prev_ripple = 9'b0;
@ -9,4 +9,35 @@ module top(input clk, input a, input b, output [9:0] x);
assign x = ripple[9] + b; assign x = ripple[9] + b;
endmodule endmodule
EOF EOF
hierarchy -top top
prep
check -assert
design -reset
read -vlog2k <<EOF
module top(clk, y, sideread_addr, sideread_data);
input wire clk;
reg [7:0] mem [255:0];
reg [8:0] i;
initial begin
for (i = 0; i < 256; i = i + 1)
mem[i] = i * 371;
end
output reg [7:0] y = 1;
always @(posedge clk)
y <= mem[y];
input wire [7:0] sideread_addr;
output wire [7:0] sideread_data;
assign sideread_data = mem[sideread_addr];
endmodule
EOF
hierarchy -top top
prep -rdff
select -assert-count 1 t:$mem_v2
check -assert
memory_unpack
select -assert-count 2 t:$memrd_v2
check -assert check -assert

17
tests/various/check_2.ys Normal file
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@ -0,0 +1,17 @@
# just so slightly adjust the example from check.ys to induce a loop
design -reset
read -vlog2k <<EOF
module top(input clk, input a, input b, output [9:0] x);
wire [9:0] ripple;
reg [9:0] prev_ripple = 9'b0;
always @(posedge clk) prev_ripple <= ripple;
assign ripple = {ripple[8:1], a, ripple[0]} ^ prev_ripple;
assign x = ripple[9] + b;
endmodule
EOF
hierarchy -top top
prep
logger -expect warning "found logic loop in module top:" 1
logger -expect error "Found 1 problems in 'check -assert'" 1
check -assert

20
tests/various/check_3.ys Normal file
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@ -0,0 +1,20 @@
# loop involving asynchronous memory ports
design -reset
read -vlog2k <<EOF
module pingpong(input wire [1:0] x, output wire [3:0] y1, output wire [3:0] y2);
reg [3:0] mem [15:0];
reg [5:0] i;
initial begin
for (i = 0; i < 16; i = i + 1)
mem[i] = i * 371;
end
assign y1 = mem[{y2[3:2], x}];
assign y2 = mem[y1];
endmodule
EOF
hierarchy -top pingpong
prep
logger -nowarn "found logic loop in module pingpong:"
logger -expect error "Found \d+ problems in 'check -assert'" 1
check -assert