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Refactor to ShregmapTechXilinx7Static

This commit is contained in:
Eddie Hung 2019-06-05 11:08:08 -07:00
parent 45d1bdf83a
commit e1e37db860
1 changed files with 86 additions and 46 deletions
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132
passes/techmap/shregmap.cc
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@ -29,7 +29,7 @@ struct ShregmapTech
virtual void init(const Module * /*module*/, const SigMap &/*sigmap*/) {} virtual void init(const Module * /*module*/, const SigMap &/*sigmap*/) {}
virtual void non_chain_user(const SigBit &/*bit*/, const Cell* /*cell*/, IdString /*port*/) {} virtual void non_chain_user(const SigBit &/*bit*/, const Cell* /*cell*/, IdString /*port*/) {}
virtual bool analyze(vector<int> &taps, const vector<SigBit> &qbits) = 0; virtual bool analyze(vector<int> &taps, const vector<SigBit> &qbits) = 0;
virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) = 0; virtual RTLIL::Cell* fixup(Cell *cell, dict<int, SigBit> &taps) = 0;
}; };
struct ShregmapOptions struct ShregmapOptions
@ -71,7 +71,7 @@ struct ShregmapTechGreenpak4 : ShregmapTech
return true; return true;
} }
virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) override virtual RTLIL::Cell* fixup(Cell *cell, dict<int, SigBit> &taps) override
{ {
auto D = cell->getPort("\\D"); auto D = cell->getPort("\\D");
auto C = cell->getPort("\\C"); auto C = cell->getPort("\\C");
@ -89,16 +89,84 @@ struct ShregmapTechGreenpak4 : ShregmapTech
} }
cell->setParam("\\OUTA_INVERT", 0); cell->setParam("\\OUTA_INVERT", 0);
return false; return newcell;
} }
}; };
struct ShregmapTechXilinx7Dynamic : ShregmapTech struct ShregmapTechXilinx7Static : ShregmapTech
{ {
dict<SigBit, std::tuple<Cell*,int,int>> sigbit_to_shiftx_offset;
const ShregmapOptions &opts; const ShregmapOptions &opts;
ShregmapTechXilinx7Dynamic(const ShregmapOptions &opts) : opts(opts) {} ShregmapTechXilinx7Static(const ShregmapOptions &opts) : opts(opts) {}
virtual bool analyze(vector<int> &taps, const vector<SigBit> &/*qbits*/) override
{
if (GetSize(taps) == 1)
return taps[0] >= opts.minlen-1;
if (taps.back() < opts.minlen-1)
return false;
return true;
}
virtual RTLIL::Cell* fixup(Cell *cell, dict<int, SigBit> &/*taps*/) override
{
auto newcell = cell->module->addCell(NEW_ID, "$__SHREG_");
newcell->set_src_attribute(cell->get_src_attribute());
newcell->setParam("\\DEPTH", cell->getParam("\\DEPTH"));
newcell->setParam("\\INIT", cell->getParam("\\INIT"));
if (cell->type.in("$__SHREG_DFF_N_", "$__SHREG_DFF_P_",
"$__SHREG_DFFE_NN_", "$__SHREG_DFFE_NP_", "$__SHREG_DFFE_PN_", "$__SHREG_DFFE_PP_")) {
int param_clkpol = -1;
int param_enpol = 2;
if (cell->type == "$__SHREG_DFF_N_") param_clkpol = 0;
else if (cell->type == "$__SHREG_DFF_P_") param_clkpol = 1;
else if (cell->type == "$__SHREG_DFFE_NN_") param_clkpol = 0, param_enpol = 0;
else if (cell->type == "$__SHREG_DFFE_NP_") param_clkpol = 0, param_enpol = 1;
else if (cell->type == "$__SHREG_DFFE_PN_") param_clkpol = 1, param_enpol = 0;
else if (cell->type == "$__SHREG_DFFE_PP_") param_clkpol = 1, param_enpol = 1;
else log_abort();
log_assert(param_clkpol >= 0);
newcell->setParam("\\CLKPOL", param_clkpol);
newcell->setParam("\\ENPOL", param_enpol);
if (cell->hasPort("\\E"))
newcell->setPort("\\E", cell->getPort("\\E"));
}
else if (cell->type.in("$__SHREG_FDRE_", "$__SHREG_FDSE_", "$__SHREG_FDCE_", "$__SHREG_FDPE_")) {
if (cell->getParam("\\IS_C_INVERTED").as_bool())
newcell->setParam("\\CLKPOL", 0);
else
newcell->setParam("\\CLKPOL", 1);
newcell->setParam("\\ENPOL", 1);
newcell->setPort("\\E", cell->getPort("\\CE"));
}
else if (cell->type.in("$__SHREG_FDRE_1_", "$__SHREG_FDSE_1_", "$__SHREG_FDCE_1_", "$__SHREG_FDPE_1_")) {
newcell->setParam("\\CLKPOL", 0);
newcell->setPort("\\E", cell->getPort("\\CE"));
}
else log_abort();
newcell->setParam("\\ENPOL", 1);
newcell->setPort("\\C", cell->getPort("\\C"));
newcell->setPort("\\D", cell->getPort("\\D"));
newcell->setPort("\\Q", cell->getPort("\\Q"));
return newcell;
}
};
struct ShregmapTechXilinx7Dynamic : ShregmapTechXilinx7Static
{
dict<SigBit, std::tuple<Cell*,int,int>> sigbit_to_shiftx_offset;
ShregmapTechXilinx7Dynamic(const ShregmapOptions &opts) : ShregmapTechXilinx7Static(opts) {}
virtual void init(const Module* module, const SigMap &sigmap) override virtual void init(const Module* module, const SigMap &sigmap) override
{ {
@ -200,7 +268,7 @@ struct ShregmapTechXilinx7Dynamic : ShregmapTech
return true; return true;
} }
virtual bool fixup(Cell *cell, dict<int, SigBit> &taps) override virtual RTLIL::Cell* fixup(Cell *cell, dict<int, SigBit> &taps) override
{ {
const auto &tap = *taps.begin(); const auto &tap = *taps.begin();
auto bit = tap.second; auto bit = tap.second;
@ -208,52 +276,24 @@ struct ShregmapTechXilinx7Dynamic : ShregmapTech
auto it = sigbit_to_shiftx_offset.find(bit); auto it = sigbit_to_shiftx_offset.find(bit);
log_assert(it != sigbit_to_shiftx_offset.end()); log_assert(it != sigbit_to_shiftx_offset.end());
auto newcell = cell->module->addCell(NEW_ID, "$__XILINX_SHREG_"); RTLIL::Cell* newcell = ShregmapTechXilinx7Static::fixup(cell, taps);
newcell->set_src_attribute(cell->get_src_attribute()); log_assert(newcell);
newcell->setParam("\\DEPTH", cell->getParam("\\DEPTH")); log_assert(newcell->type == "$__SHREG_");
newcell->setParam("\\INIT", cell->getParam("\\INIT")); newcell->type = "$__XILINX_SHREG_";
if (cell->type.in("$__SHREG_DFF_N_", "$__SHREG_DFF_P_",
"$__SHREG_DFFE_NN_", "$__SHREG_DFFE_NP_", "$__SHREG_DFFE_PN_", "$__SHREG_DFFE_PP_")) {
int param_clkpol = -1;
int param_enpol = 2;
if (cell->type == "$__SHREG_DFF_N_") param_clkpol = 0;
else if (cell->type == "$__SHREG_DFF_P_") param_clkpol = 1;
else if (cell->type == "$__SHREG_DFFE_NN_") param_clkpol = 0, param_enpol = 0;
else if (cell->type == "$__SHREG_DFFE_NP_") param_clkpol = 0, param_enpol = 1;
else if (cell->type == "$__SHREG_DFFE_PN_") param_clkpol = 1, param_enpol = 0;
else if (cell->type == "$__SHREG_DFFE_PP_") param_clkpol = 1, param_enpol = 1;
else log_abort();
log_assert(param_clkpol >= 0);
cell->setParam("\\CLKPOL", param_clkpol);
cell->setParam("\\ENPOL", param_enpol);
}
else log_abort();
newcell->setPort("\\C", cell->getPort("\\C"));
newcell->setPort("\\D", cell->getPort("\\D"));
if (cell->hasPort("\\E"))
newcell->setPort("\\E", cell->getPort("\\E"));
Cell* shiftx = std::get<0>(it->second); Cell* shiftx = std::get<0>(it->second);
RTLIL::SigSpec l_wire, q_wire; RTLIL::SigSpec l_wire;
if (shiftx->type == "$shiftx") { if (shiftx->type == "$shiftx")
l_wire = shiftx->getPort("\\B"); l_wire = shiftx->getPort("\\B");
q_wire = shiftx->getPort("\\Y"); else if (shiftx->type == "$mux")
shiftx->setPort("\\Y", cell->module->addWire(NEW_ID));
}
else if (shiftx->type == "$mux") {
l_wire = shiftx->getPort("\\S"); l_wire = shiftx->getPort("\\S");
q_wire = shiftx->getPort("\\Y");
shiftx->setPort("\\Y", cell->module->addWire(NEW_ID));
}
else log_abort(); else log_abort();
newcell->setPort("\\Q", q_wire);
newcell->setPort("\\L", l_wire); newcell->setPort("\\L", l_wire);
newcell->setPort("\\Q", shiftx->getPort("\\Y"));
shiftx->setPort("\\Y", cell->module->addWire(NEW_ID));
return false; return newcell;
} }
}; };
@ -509,7 +549,7 @@ struct ShregmapWorker
first_cell->setPort(q_port, last_cell->getPort(q_port)); first_cell->setPort(q_port, last_cell->getPort(q_port));
first_cell->setParam("\\DEPTH", depth); first_cell->setParam("\\DEPTH", depth);
if (opts.tech != nullptr && !opts.tech->fixup(first_cell, taps_dict)) if (opts.tech != nullptr && opts.tech->fixup(first_cell, taps_dict))
remove_cells.insert(first_cell); remove_cells.insert(first_cell);
for (int i = 1; i < depth; i++) for (int i = 1; i < depth; i++)