mirror of https://github.com/YosysHQ/yosys.git
Added "test_cell -script"
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@ -380,6 +380,9 @@ struct TestCellPass : public Pass {
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log(" -simplib\n");
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log(" use \"techmap -map +/simlib.v -max_iter 2 -autoproc\"\n");
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log("\n");
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log(" -script {script_file}\n");
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log(" instead of calling \"techmap\", call \"script {script_file}\".\n");
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log("\n");
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log(" -v\n");
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log(" print additional debug information to the console\n");
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log("\n");
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@ -416,6 +419,10 @@ struct TestCellPass : public Pass {
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num_iter = 1;
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continue;
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}
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if (args[argidx] == "-script" && argidx+1 < SIZE(args)) {
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techmap_cmd = "script " + args[++argidx];
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continue;
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}
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if (args[argidx] == "-simlib") {
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techmap_cmd = "techmap -map +/simlib.v -max_iter 2 -autoproc";
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continue;
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@ -540,7 +547,7 @@ struct TestCellPass : public Pass {
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Frontend::frontend_call(design, NULL, std::string(), "ilang " + ilang_file);
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else
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create_gold_module(design, cell_type, cell_types.at(cell_type));
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Pass::call(design, stringf("copy gold gate; %s gate; opt gate", techmap_cmd.c_str()));
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Pass::call(design, stringf("copy gold gate; cd gate; %s; cd ..; opt -fast gate", techmap_cmd.c_str()));
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Pass::call(design, "miter -equiv -flatten -make_outputs -ignore_gold_x gold gate miter");
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if (verbose)
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Pass::call(design, "dump gate");
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