riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Added "test_cell -script"

This commit is contained in:
Clifford Wolf 2014-09-06 11:46:07 +02:00
parent f5a40e7043
commit e1743b3bac
1 changed files with 8 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
passes/tests/test_cell.cc
View File

@ -380,6 +380,9 @@ struct TestCellPass : public Pass {
log(" -simplib\n"); log(" -simplib\n");
log(" use \"techmap -map +/simlib.v -max_iter 2 -autoproc\"\n"); log(" use \"techmap -map +/simlib.v -max_iter 2 -autoproc\"\n");
log("\n"); log("\n");
log(" -script {script_file}\n");
log(" instead of calling \"techmap\", call \"script {script_file}\".\n");
log("\n");
log(" -v\n"); log(" -v\n");
log(" print additional debug information to the console\n"); log(" print additional debug information to the console\n");
log("\n"); log("\n");
@ -416,6 +419,10 @@ struct TestCellPass : public Pass {
num_iter = 1; num_iter = 1;
continue; continue;
} }
if (args[argidx] == "-script" && argidx+1 < SIZE(args)) {
techmap_cmd = "script " + args[++argidx];
continue;
}
if (args[argidx] == "-simlib") { if (args[argidx] == "-simlib") {
techmap_cmd = "techmap -map +/simlib.v -max_iter 2 -autoproc"; techmap_cmd = "techmap -map +/simlib.v -max_iter 2 -autoproc";
continue; continue;
@ -540,7 +547,7 @@ struct TestCellPass : public Pass {
Frontend::frontend_call(design, NULL, std::string(), "ilang " + ilang_file); Frontend::frontend_call(design, NULL, std::string(), "ilang " + ilang_file);
else else
create_gold_module(design, cell_type, cell_types.at(cell_type)); create_gold_module(design, cell_type, cell_types.at(cell_type));
Pass::call(design, stringf("copy gold gate; %s gate; opt gate", techmap_cmd.c_str())); Pass::call(design, stringf("copy gold gate; cd gate; %s; cd ..; opt -fast gate", techmap_cmd.c_str()));
Pass::call(design, "miter -equiv -flatten -make_outputs -ignore_gold_x gold gate miter"); Pass::call(design, "miter -equiv -flatten -make_outputs -ignore_gold_x gold gate miter");
if (verbose) if (verbose)
Pass::call(design, "dump gate"); Pass::call(design, "dump gate");