mirror of https://github.com/YosysHQ/yosys.git
Fixed typo in RTLIL::Module::addAdff()
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@ -1096,7 +1096,7 @@ RTLIL::Cell* RTLIL::Module::addAdff(RTLIL::IdString name, RTLIL::SigSpec sig_clk
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{
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{
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RTLIL::Cell *cell = new RTLIL::Cell;
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RTLIL::Cell *cell = new RTLIL::Cell;
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cell->name = name;
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cell->name = name;
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cell->type = "$dffsr";
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cell->type = "$adff";
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cell->parameters["\\CLK_POLARITY"] = clk_polarity;
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cell->parameters["\\CLK_POLARITY"] = clk_polarity;
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cell->parameters["\\ARST_POLARITY"] = arst_polarity;
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cell->parameters["\\ARST_POLARITY"] = arst_polarity;
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cell->parameters["\\ARST_VALUE"] = arst_value;
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cell->parameters["\\ARST_VALUE"] = arst_value;
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