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Fix LUT6_2 definition. 

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
This commit is contained in:
Keith Rothman 2019-04-09 11:43:19 -07:00
parent 5e0339855f
commit e107ccdde8
1 changed files with 3 additions and 3 deletions
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6
techlibs/xilinx/cells_sim.v
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@ -149,9 +149,9 @@ module LUT6_2(output O6, output O5, input I0, I1, I2, I3, I4, I5);
assign O6 = I0 ? s1[1] : s1[0]; assign O6 = I0 ? s1[1] : s1[0];
wire [15: 0] s5_4 = I4 ? INIT[31:16] : INIT[15: 0]; wire [15: 0] s5_4 = I4 ? INIT[31:16] : INIT[15: 0];
wire [ 7: 0] s5_3 = I3 ? s4[15: 8] : s4[ 7: 0]; wire [ 7: 0] s5_3 = I3 ? s5_4[15: 8] : s5_4[ 7: 0];
wire [ 3: 0] s5_2 = I2 ? s3[ 7: 4] : s3[ 3: 0]; wire [ 3: 0] s5_2 = I2 ? s5_3[ 7: 4] : s5_3[ 3: 0];
wire [ 1: 0] s5_1 = I1 ? s2[ 3: 2] : s2[ 1: 0]; wire [ 1: 0] s5_1 = I1 ? s5_2[ 3: 2] : s5_2[ 1: 0];
assign O5 = I0 ? s5_1[1] : s5_1[0]; assign O5 = I0 ? s5_1[1] : s5_1[0];
endmodule endmodule