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fix iverilog compatibility for new case expr tests

This commit is contained in:
Zachary Snow 2021-12-29 10:38:55 -07:00 committed by Zachary Snow
parent 207af4196b
commit e0e4dfb55e
2 changed files with 2 additions and 2 deletions
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2
tests/simple/case_expr_extend.sv
View File

@ -1,7 +1,7 @@
module top( module top(
output logic [5:0] out output logic [5:0] out
); );
always_comb begin initial begin
out = '0; out = '0;
case (1'b1 << 1) case (1'b1 << 1)
2'b10: out = '1; 2'b10: out = '1;

2
tests/simple/case_expr_query.sv
View File

@ -1,7 +1,7 @@
module top( module top(
output logic [5:0] out output logic [5:0] out
); );
always_comb begin initial begin
out = '0; out = '0;
case ($bits (out)) 6: case ($bits (out)) 6:
case ($size (out)) 6: case ($size (out)) 6: