mirror of https://github.com/YosysHQ/yosys.git
Check abc_box_id attr
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8fbbd9b129
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@ -212,6 +212,8 @@ struct XAigerWriter
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continue;
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}
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bool abc_box = module->design->module(cell->type)->attributes.count("\\abc_box_id");
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for (const auto &c : cell->connections()) {
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/*if (c.second.is_fully_const()) continue;*/
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for (auto b : c.second.bits()) {
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@ -224,20 +226,33 @@ struct XAigerWriter
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if (I != b)
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alias_map[b] = I;
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/*if (!output_bits.count(b))*/
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if (abc_box)
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co_bits.emplace_back(b, 0);
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else {
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output_bits.insert(b);
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if (!b.wire->port_input)
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unused_bits.erase(b);
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}
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}
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}
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if (is_output) {
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SigBit O = sigmap(b);
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/*if (!input_bits.count(O))*/
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if (abc_box)
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ci_bits.emplace_back(O, 0);
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else {
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input_bits.insert(O);
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if (!O.wire->port_output)
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undriven_bits.erase(O);
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}
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}
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}
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if (!type_map.count(cell->type))
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type_map[cell->type] = type_map.size()+1;
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}
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box_list.emplace_back(cell);
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if (abc_box)
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box_list.emplace_back(cell);
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//log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
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}
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