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Uncomment out more tests
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@ -63,30 +63,44 @@ always @(io or oe)
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assign io = oe ? ~latch : 8'bz;
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assign io = oe ? ~latch : 8'bz;
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endmodule
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endmodule
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// TODO
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module abc9_test011(inout io, input oe);
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//module abc9_test011(inout [7:0] io, input oe);
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reg latch;
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//reg [7:0] latch;
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always @(io or oe)
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//always @(io or oe)
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if (!oe)
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// if (!oe)
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latch <= io;
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// latch[3:0] <= io;
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//assign io = oe ? ~latch : 8'bz;
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// else
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endmodule
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// latch[7:4] <= io;
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//assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
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//assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
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//endmodule
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// TODO
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module abc9_test012(inout io, input oe);
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//module abc9_test012(inout [7:0] io, input oe);
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reg latch;
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//abc9_test012_sub sub(io, oe);
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//endmodule
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//
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//module abc9_test012_sub(inout [7:0] io, input oe);
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//reg [7:0] latch;
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//always @(io or oe)
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//always @(io or oe)
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// if (!oe)
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// if (!oe)
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// latch[3:0] <= io;
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// latch <= io;
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// else
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assign io = oe ? ~latch : 8'bz;
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// latch[7:4] <= io;
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endmodule
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//assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
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//assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
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module abc9_test013(inout [3:0] io, input oe);
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//endmodule
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reg [3:0] latch;
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always @(io or oe)
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if (!oe)
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latch[3:0] <= io[3:0];
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else
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latch[7:4] <= io;
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assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
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assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
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endmodule
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module abc9_test014(inout [7:0] io, input oe);
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abc9_test012_sub sub(io, oe);
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endmodule
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module abc9_test012_sub(inout [7:0] io, input oe);
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reg [7:0] latch;
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always @(io or oe)
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if (!oe)
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latch[3:0] <= io;
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else
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latch[7:4] <= io;
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assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
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assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
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endmodule
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