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Added test case for AstNode::MEM2REG_FL_CMPLX_LHS

This commit is contained in:
Clifford Wolf 2014-06-17 21:49:59 +02:00
parent 80e4594695
commit df76da8fd7
1 changed files with 12 additions and 0 deletions
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12
tests/simple/mem2reg.v
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@ -43,3 +43,15 @@ end
endmodule endmodule
// ------------------------------------------------------
// http://www.reddit.com/r/yosys/comments/28d9lx/problem_with_concatenation_of_two_dimensional/
module test3( input clk, input [8:0] din_a, output reg [7:0] dout_a, output [7:0] dout_b);
reg [7:0] dint_c [0:7];
always @(posedge clk)
begin
{dout_a[0], dint_c[3]} <= din_a;
end
assign dout_b = dint_c[3];
endmodule