mirror of https://github.com/YosysHQ/yosys.git
Fixed bug in equiv_miter
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parent
23e54bda81
commit
df64542288
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@ -218,9 +218,9 @@ struct EquivMiterWorker
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for (auto c : equiv_cells)
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{
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SigSpec trigger = mode_undef ?
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miter_module->Mux(NEW_ID, miter_module->Eqx(NEW_ID, c->getPort("\\A"), c->getPort("\\B")),
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State::S1, miter_module->Eqx(NEW_ID, c->getPort("\\A"), State::Sx)) :
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SigSpec cmp = mode_undef ?
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miter_module->LogicOr(NEW_ID, miter_module->Eqx(NEW_ID, c->getPort("\\A"), State::Sx),
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miter_module->Eqx(NEW_ID, c->getPort("\\A"), c->getPort("\\B"))) :
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miter_module->Eq(NEW_ID, c->getPort("\\A"), c->getPort("\\B"));
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if (mode_cmp) {
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@ -232,13 +232,13 @@ struct EquivMiterWorker
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cmp_name = cmp_name.substr(0, i) + cmp_name.substr(i+1);
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auto w = miter_module->addWire(cmp_name);
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w->port_output = true;
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miter_module->connect(w, trigger);
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miter_module->connect(w, cmp);
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}
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if (mode_assert)
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miter_module->addAssert(NEW_ID, miter_module->Not(NEW_ID, trigger), State::S1);
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miter_module->addAssert(NEW_ID, cmp, State::S1);
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trigger_signals.append(trigger);
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trigger_signals.append(miter_module->Not(NEW_ID, cmp));
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}
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if (mode_trigger) {
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