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Renamed module parameter

This commit is contained in:
Andrew Zonenberg 2016-05-04 17:03:45 -07:00
parent a613f171ae
commit dee1c27a19
1 changed files with 4 additions and 4 deletions
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8
techlibs/greenpak4/cells_sim.v
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@ -278,9 +278,9 @@ endmodule
module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB); module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
parameter OUTA_DELAY = 1; parameter OUTA_TAP = 1;
parameter OUTA_INVERT = 0; parameter OUTA_INVERT = 0;
parameter OUTB_DELAY = 1; parameter OUTB_TAP = 1;
reg[15:0] shreg = 0; reg[15:0] shreg = 0;
@ -294,8 +294,8 @@ module GP_SHREG(input nRST, input CLK, input IN, output OUTA, output OUTB);
end end
assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_DELAY - 1] : shreg[OUTA_DELAY - 1]; assign OUTA = (OUTA_INVERT) ? ~shreg[OUTA_TAP - 1] : shreg[OUTA_TAP - 1];
assign OUTB = shreg[OUTB_DELAY - 1]; assign OUTB = shreg[OUTB_TAP - 1];
endmodule endmodule