mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #2443 from YosysHQ/dave/nexus-mult-infer
nexus: Multiplier inference support
This commit is contained in:
Miodrag Milanović
GitHub
commit
de58e774ef
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@ -11,4 +11,5 @@ $(eval $(call add_share_file,share/nexus,techlibs/nexus/brams_map.v))
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$(eval $(call add_share_file,share/nexus,techlibs/nexus/brams.txt))
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$(eval $(call add_share_file,share/nexus,techlibs/nexus/arith_map.v))
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$(eval $(call add_share_file,share/nexus,techlibs/nexus/latches_map.v))
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$(eval $(call add_share_file,share/nexus,techlibs/nexus/dsp_map.v))
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@ -0,0 +1,79 @@
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module \$__NX_MUL36X36 (input [35:0] A, input [35:0] B, output [71:0] Y);
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parameter A_WIDTH = 36;
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parameter B_WIDTH = 36;
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parameter Y_WIDTH = 72;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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MULT36X36 #(
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.REGINPUTA("BYPASS"),
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.REGINPUTB("BYPASS"),
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.REGOUTPUT("BYPASS")
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) _TECHMAP_REPLACE_ (
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.A(A), .B(B),
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.SIGNEDA(A_SIGNED ? 1'b1 : 1'b0),
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.SIGNEDB(B_SIGNED ? 1'b1 : 1'b0),
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.Z(Y)
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);
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endmodule
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module \$__NX_MUL36X18 (input [35:0] A, input [17:0] B, output [53:0] Y);
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parameter A_WIDTH = 36;
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parameter B_WIDTH = 18;
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parameter Y_WIDTH = 54;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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MULT18X36 #(
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.REGINPUTA("BYPASS"),
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.REGINPUTB("BYPASS"),
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.REGOUTPUT("BYPASS")
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) _TECHMAP_REPLACE_ (
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.A(B), .B(A),
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.SIGNEDA(B_SIGNED ? 1'b1 : 1'b0),
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.SIGNEDB(A_SIGNED ? 1'b1 : 1'b0),
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.Z(Y)
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);
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endmodule
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module \$__NX_MUL18X18 (input [17:0] A, input [17:0] B, output [35:0] Y);
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parameter A_WIDTH = 18;
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parameter B_WIDTH = 18;
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parameter Y_WIDTH = 36;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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MULT18X18 #(
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.REGINPUTA("BYPASS"),
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.REGINPUTB("BYPASS"),
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.REGOUTPUT("BYPASS")
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) _TECHMAP_REPLACE_ (
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.A(A), .B(B),
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.SIGNEDA(A_SIGNED ? 1'b1 : 1'b0),
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.SIGNEDB(B_SIGNED ? 1'b1 : 1'b0),
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.Z(Y)
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);
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endmodule
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module \$__NX_MUL9X9 (input [8:0] A, input [8:0] B, output [17:0] Y);
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parameter A_WIDTH = 9;
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parameter B_WIDTH = 9;
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parameter Y_WIDTH = 18;
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parameter A_SIGNED = 0;
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parameter B_SIGNED = 0;
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MULT9X9 #(
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.REGINPUTA("BYPASS"),
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.REGINPUTB("BYPASS"),
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.REGOUTPUT("BYPASS")
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) _TECHMAP_REPLACE_ (
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.A(A), .B(B),
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.SIGNEDA(A_SIGNED ? 1'b1 : 1'b0),
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.SIGNEDB(B_SIGNED ? 1'b1 : 1'b0),
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.Z(Y)
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);
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endmodule
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@ -89,6 +89,9 @@ struct SynthNexusPass : public ScriptPass
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log(" -noiopad\n");
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log(" do not insert IO buffers\n");
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log("\n");
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log(" -nodsp\n");
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log(" do not infer DSP multipliers\n");
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log("\n");
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log(" -abc9\n");
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log(" use new ABC9 flow (EXPERIMENTAL)\n");
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log("\n");
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@ -98,7 +101,7 @@ struct SynthNexusPass : public ScriptPass
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}
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string top_opt, json_file, vm_file, family;
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bool noccu2, nodffe, nobram, nolutram, nowidelut, noiopad, flatten, dff, retime, abc9;
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bool noccu2, nodffe, nobram, nolutram, nowidelut, noiopad, nodsp, flatten, dff, retime, abc9;
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void clear_flags() override
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{
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@ -112,6 +115,7 @@ struct SynthNexusPass : public ScriptPass
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nolutram = false;
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nowidelut = false;
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noiopad = false;
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nodsp = false;
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flatten = true;
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dff = false;
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retime = false;
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@ -161,6 +165,10 @@ struct SynthNexusPass : public ScriptPass
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dff = true;
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continue;
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}
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if (args[argidx] == "-nodsp") {
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nodsp = true;
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continue;
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}
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if (args[argidx] == "-retime") {
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retime = true;
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continue;
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@ -211,6 +219,22 @@ struct SynthNexusPass : public ScriptPass
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log_pop();
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}
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struct DSPRule {
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int a_maxwidth;
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int b_maxwidth;
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int a_minwidth;
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int b_minwidth;
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std::string prim;
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};
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const std::vector<DSPRule> dsp_rules = {
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{36, 36, 22, 22, "$__NX_MUL36X36"},
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{36, 18, 22, 10, "$__NX_MUL36X18"},
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{18, 18, 10, 4, "$__NX_MUL18X18"},
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{18, 18, 4, 10, "$__NX_MUL18X18"},
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{ 9, 9, 4, 4, "$__NX_MUL9X9"},
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};
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void script() override
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{
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@ -244,6 +268,18 @@ struct SynthNexusPass : public ScriptPass
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run("opt_expr");
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run("opt_clean");
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if (help_mode) {
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run("techmap -map +/mul2dsp.v [...]", "(unless -nodsp)");
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run("techmap -map +/nexus/dsp_map.v", "(unless -nodsp)");
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} else if (!nodsp) {
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for (const auto &rule : dsp_rules) {
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run(stringf("techmap -map +/mul2dsp.v -D DSP_A_MAXWIDTH=%d -D DSP_B_MAXWIDTH=%d -D DSP_A_MINWIDTH=%d -D DSP_B_MINWIDTH=%d -D DSP_NAME=%s",
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rule.a_maxwidth, rule.b_maxwidth, rule.a_minwidth, rule.b_minwidth, rule.prim.c_str()));
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run("chtype -set $mul t:$__soft_mul");
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}
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run("techmap -map +/nexus/dsp_map.v");
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}
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run("alumacc");
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run("opt");
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run("memory -nomap");
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@ -1,4 +1,5 @@
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 8 -set Y_WIDTH 8 -set A_WIDTH 16
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hierarchy -top top
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proc
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@ -7,22 +8,43 @@ design -save read
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equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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select -assert-count 7 t:CCU2
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select -assert-max 5 t:WIDEFN9
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select -assert-max 62 t:LUT4
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select -assert-count 1 t:MULT9X9
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select -assert-none t:IB t:OB t:VLO t:VHI t:LUT4 t:CCU2 t:WIDEFN9 %% t:* %D
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select -assert-none t:IB t:OB t:VLO t:VHI t:MULT9X9 %% t:* %D
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design -load read
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equiv_opt -assert -map +/nexus/cells_sim.v synth_nexus -abc9
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 16 -set Y_WIDTH 16 -set A_WIDTH 32
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hierarchy -top top
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proc
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# equivalence checking is too slow here
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synth_nexus
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MULT18X18
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select -assert-none t:IB t:OB t:VLO t:VHI t:MULT18X18 %% t:* %D
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stat
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select -assert-count 7 t:CCU2
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select -assert-max 12 t:WIDEFN9
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select -assert-max 58 t:LUT4
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 32 -set Y_WIDTH 16 -set A_WIDTH 48
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hierarchy -top top
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proc
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# equivalence checking is too slow here
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synth_nexus
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MULT18X36
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select -assert-none t:IB t:OB t:VLO t:VHI t:MULT18X36 %% t:* %D
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select -assert-none t:IB t:OB t:VLO t:VHI t:LUT4 t:CCU2 t:WIDEFN9 %% t:* %D
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design -reset
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read_verilog ../common/mul.v
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chparam -set X_WIDTH 32 -set Y_WIDTH 32 -set A_WIDTH 64
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hierarchy -top top
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proc
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# equivalence checking is too slow here
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synth_nexus
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cd top # Constrain all select calls below inside the top module
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select -assert-count 1 t:MULT36X36
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select -assert-none t:IB t:OB t:VLO t:VHI t:MULT36X36 %% t:* %D
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