mirror of https://github.com/YosysHQ/yosys.git
sim: New -append option for Yosys witness cosim
This is needed to support SBY's append option.
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2dd5652215
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dda972a148
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@ -1735,7 +1735,7 @@ struct SimWorker : SimShared
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}
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}
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void run_cosim_yw_witness(Module *topmod)
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void run_cosim_yw_witness(Module *topmod, int append)
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{
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if (!clock.empty())
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log_cmd_error("The -clock option is not required nor supported when reading a Yosys witness file.\n");
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@ -1770,10 +1770,11 @@ struct SimWorker : SimShared
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top->set_initstate_outputs(State::S0);
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}
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for (int cycle = 1; cycle < GetSize(yw.steps); cycle++)
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for (int cycle = 1; cycle < GetSize(yw.steps) + append; cycle++)
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{
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if (verbose)
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log("Simulating cycle %d.\n", cycle);
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if (cycle < GetSize(yw.steps))
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set_yw_state(yw, hierarchy, cycle);
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set_yw_clocks(yw, hierarchy, true);
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update(true);
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@ -1788,7 +1789,7 @@ struct SimWorker : SimShared
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}
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}
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register_output_step(10*GetSize(yw.steps));
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register_output_step(10 * (GetSize(yw.steps) + append));
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write_output_files();
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}
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@ -2326,6 +2327,9 @@ struct SimPass : public Pass {
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log(" File formats supported: FST, VCD, AIW, WIT and .yw\n");
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log(" VCD support requires vcd2fst external tool to be present\n");
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log("\n");
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log(" -append <integer>\n");
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log(" number of extra clock cycles to simulate for a Yosys witness input\n");
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log("\n");
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log(" -map <filename>\n");
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log(" read file with port and latch symbols, needed for AIGER witness input\n");
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log("\n");
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@ -2371,6 +2375,7 @@ struct SimPass : public Pass {
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{
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SimWorker worker;
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int numcycles = 20;
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int append = 0;
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bool start_set = false, stop_set = false, at_set = false;
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log_header(design, "Executing SIM pass (simulate the circuit).\n");
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@ -2454,6 +2459,10 @@ struct SimPass : public Pass {
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worker.sim_filename = sim_filename;
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continue;
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}
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if (args[argidx] == "-append" && argidx+1 < args.size()) {
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append = atoi(args[++argidx].c_str());
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continue;
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}
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if (args[argidx] == "-map" && argidx+1 < args.size()) {
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std::string map_filename = args[++argidx];
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rewrite_filename(map_filename);
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@ -2544,7 +2553,7 @@ struct SimPass : public Pass {
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} else if (filename_trim.size() > 4 && filename_trim.compare(filename_trim.size()-4, std::string::npos, ".wit") == 0) {
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worker.run_cosim_btor2_witness(top_mod);
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} else if (filename_trim.size() > 3 && filename_trim.compare(filename_trim.size()-3, std::string::npos, ".yw") == 0) {
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worker.run_cosim_yw_witness(top_mod);
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worker.run_cosim_yw_witness(top_mod, append);
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} else {
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log_cmd_error("Unhandled extension for simulation input file `%s`.\n", worker.sim_filename.c_str());
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}
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