riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

blackbox: Include whiteboxed modules 

Signed-off-by: gatecat <gatecat@ds0.me>
This commit is contained in:
gatecat 2021-03-17 12:06:09 +00:00
parent 937392ad33
commit dd6d34f461
4 changed files with 19 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
kernel/rtlil.cc
View File

@ -808,12 +808,12 @@ std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules() const
return result; return result;
} }
std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn() const std::vector<RTLIL::Module*> RTLIL::Design::selected_whole_modules_warn(bool include_wb) const
{ {
std::vector<RTLIL::Module*> result; std::vector<RTLIL::Module*> result;
result.reserve(modules_.size()); result.reserve(modules_.size());
for (auto &it : modules_) for (auto &it : modules_)
if (it.second->get_blackbox_attribute()) if (it.second->get_blackbox_attribute(include_wb))
continue; continue;
else if (selected_whole_module(it.first)) else if (selected_whole_module(it.first))
result.push_back(it.second); result.push_back(it.second);

2
kernel/rtlil.h
View File

@ -1112,7 +1112,7 @@ struct RTLIL::Design
std::vector<RTLIL::Module*> selected_modules() const; std::vector<RTLIL::Module*> selected_modules() const;
std::vector<RTLIL::Module*> selected_whole_modules() const; std::vector<RTLIL::Module*> selected_whole_modules() const;
std::vector<RTLIL::Module*> selected_whole_modules_warn() const; std::vector<RTLIL::Module*> selected_whole_modules_warn(bool include_wb = false) const;
#ifdef WITH_PYTHON #ifdef WITH_PYTHON
static std::map<unsigned int, RTLIL::Design*> *get_all_designs(void); static std::map<unsigned int, RTLIL::Design*> *get_all_designs(void);
#endif #endif

3
passes/cmds/blackbox.cc
View File

@ -46,10 +46,11 @@ struct BlackboxPass : public Pass {
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);
for (auto module : design->selected_whole_modules_warn()) for (auto module : design->selected_whole_modules_warn(true))
{ {
module->makeblackbox(); module->makeblackbox();
module->set_bool_attribute(ID::blackbox); module->set_bool_attribute(ID::blackbox);
module->set_bool_attribute(ID::whitebox, false);
} }
} }
} BlackboxPass; } BlackboxPass;

14
tests/various/blackbox_wb.ys Normal file
View File

@ -0,0 +1,14 @@
read_verilog <<EOT
(* whitebox *)
module box(input a, output q);
assign q = ~a;
endmodule
module top(input a, output q);
box box_i(.a(a), .q(q));
endmodule
EOT
select -assert-count 1 =box/t:$not
blackbox =box
select -assert-count 0 =A:whitebox
select -assert-count 0 =box/t:$not