mirror of https://github.com/YosysHQ/yosys.git
Revert "Merge branch 'eddie/split_shiftx' into xc7mux"
This reverts commit3042d58330, reversing changes made tofeff976454.
This commit is contained in:
Eddie Hung
parent
8469d9fe9f
commit
dcc8a13e48
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@ -370,7 +370,7 @@ Verilog Attributes and non-standard features
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- When defining a macro with `define, all text between triple double quotes
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is interpreted as macro body, even if it contains unescaped newlines. The
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triple double quotes are removed from the macro body. For example:
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tipple double quotes are removed from the macro body. For example:
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`define MY_MACRO(a, b) """
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assign a = 23;
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@ -457,7 +457,7 @@ Non-standard or SystemVerilog features for formal verification
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supported in any clocked block.
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- The syntax ``@($global_clock)`` can be used to create FFs that have no
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explicit clock input (``$ff`` cells). The same can be achieved by using
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explicit clock input ($ff cells). The same can be achieved by using
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``@(posedge <netname>)`` or ``@(negedge <netname>)`` when ``<netname>``
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is marked with the ``(* gclk *)`` Verilog attribute.
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@ -470,7 +470,7 @@ from SystemVerilog:
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- The ``assert`` statement from SystemVerilog is supported in its most basic
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form. In module context: ``assert property (<expression>);`` and within an
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always block: ``assert(<expression>);``. It is transformed to an ``$assert`` cell.
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always block: ``assert(<expression>);``. It is transformed to a $assert cell.
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- The ``assume``, ``restrict``, and ``cover`` statements from SystemVerilog are
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also supported. The same limitations as with the ``assert`` statement apply.
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@ -453,7 +453,7 @@ Aig::Aig(Cell *cell)
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int B = mk.inport("\\B");
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int C = mk.inport("\\C");
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int D = mk.inport("\\D");
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int Y = mk.nand_gate(mk.or_gate(A, B), mk.or_gate(C, D));
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int Y = mk.nand_gate(mk.nor_gate(A, B), mk.nor_gate(C, D));
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mk.outport(Y, "\\Y");
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goto optimize;
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}
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@ -464,7 +464,7 @@ struct CellTypes
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if (cell->type == "$_AOI4_")
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return eval_not(const_or(const_and(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1));
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if (cell->type == "$_OAI4_")
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return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_or(arg3, arg4, false, false, 1), false, false, 1));
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return eval_not(const_and(const_or(arg1, arg2, false, false, 1), const_and(arg3, arg4, false, false, 1), false, false, 1));
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log_assert(arg4.bits.size() == 0);
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return eval(cell, arg1, arg2, arg3, errp);
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@ -462,10 +462,12 @@ struct WreduceWorker
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SigSpec initsig = init_attr_sigmap(w);
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int width = std::min(GetSize(initval), GetSize(initsig));
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for (int i = 0; i < width; i++) {
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log_dump(initsig[i], remove_init_bits.count(initsig[i]));
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if (!remove_init_bits.count(initsig[i]))
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new_initval[i] = initval[i];
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}
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w->attributes.at("\\init") = new_initval;
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log_dump(w->name, initval, new_initval);
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}
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}
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}
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@ -1 +1 @@
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*_pm.h
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/ice40_dsp_pm.h
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@ -1,11 +1,8 @@
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PMG_SRC = $(wildcard passes/pmgen/*.pmg)
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PMG_OBJS += $(patsubst %.pmg, %.o, $(PMG_SRC))
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OBJS += $(PMG_OBJS)
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OBJS += passes/pmgen/ice40_dsp.o
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$(PMG_OBJS): %.o: %_pm.h
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passes/pmgen/ice40_dsp.o: passes/pmgen/ice40_dsp_pm.h
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EXTRA_OBJS += passes/pmgen/ice40_dsp_pm.h
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.SECONDARY: passes/pmgen/ice40_dsp_pm.h
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EXTRA_OBJS += $(patsubst %.pmg, %_pm.h, $(PMG_SRC))
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.SECONDARY: $(EXTRA_OBJS)
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%_pm.h: passes/pmgen/pmgen.py %.pmg
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passes/pmgen/ice40_dsp_pm.h: passes/pmgen/pmgen.py passes/pmgen/ice40_dsp.pmg
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$(P) mkdir -p passes/pmgen && python3 $^ $@
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@ -220,5 +220,5 @@ But in some cases it is more natural to utilize the implicit branch statement:
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portAB = \B;
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endcode
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There is an implicit `code..endcode` block at the end of each `.pmg` file
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There is an implicit `code..endcode` block at the end of each `.pgm` file
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that just accepts everything that gets all the way there.
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@ -1,84 +0,0 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "passes/pmgen/split_shiftx_pm.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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void create_split_shiftx(split_shiftx_pm &pm)
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{
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log_assert(pm.st.shiftx);
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if (pm.blacklist_cells.count(pm.st.shiftx))
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return;
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SigSpec A = pm.st.shiftx->getPort("\\A");
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SigSpec B = pm.st.shiftxB;
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log_assert(!B.empty());
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SigSpec Y = pm.st.shiftx->getPort("\\Y");
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const int A_WIDTH = pm.st.shiftx->getParam("\\A_WIDTH").as_int();
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const int B_WIDTH = GetSize(pm.st.shiftxB);
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const int Y_WIDTH = pm.st.shiftx->getParam("\\Y_WIDTH").as_int();
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int trailing_zeroes = 0;
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for (; B[trailing_zeroes] == RTLIL::S0; ++trailing_zeroes) ;
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const int WIDTH = trailing_zeroes > 0 ? 1 << trailing_zeroes : Y_WIDTH;
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std::vector<SigBit> bits;
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bits.resize(A_WIDTH / WIDTH);
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for (int i = 0; i < Y_WIDTH; ++i) {
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for (int j = 0; j < A_WIDTH/WIDTH; ++j)
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bits[j] = A[j*WIDTH + i];
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pm.module->addShiftx(NEW_ID, bits, B.extract(trailing_zeroes, B_WIDTH-trailing_zeroes), Y[i]);
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}
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pm.st.shiftx->unsetPort("\\Y");
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pm.autoremove(pm.st.shiftx);
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pm.autoremove(pm.st.macc);
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}
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struct BitblastShiftxPass : public Pass {
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BitblastShiftxPass() : Pass("split_shiftx", "Split up multi-bit $shiftx cells") { }
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void help() YS_OVERRIDE
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{
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// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
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log("\n");
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log(" split_shiftx [selection]\n");
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log("\n");
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log("Split up $shiftx cells where Y_WIDTH > 1, with consideration for any $macc\n");
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log("cells -- configured as a constant multiplier equal to Y_WIDTH -- that may be\n");
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log("driving their B inputs.\n");
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log("\n");
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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log_header(design, "Executing SPLIT_SHIFTX pass.\n");
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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break;
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}
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extra_args(args, argidx, design);
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for (auto module : design->selected_modules())
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split_shiftx_pm(module, module->selected_cells()).run(create_split_shiftx);
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}
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} BitblastShiftxPass;
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PRIVATE_NAMESPACE_END
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@ -1,59 +0,0 @@
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state <SigSpec> shiftxB
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match shiftx
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select shiftx->type == $shiftx
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select param(shiftx, \Y_WIDTH).as_int() > 1
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endmatch
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match macc
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select macc->type == $macc
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select param(macc, \B_WIDTH).as_int() == 0
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optional
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endmatch
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code shiftxB
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shiftxB = port(shiftx, \B);
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if (macc) {
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const int b_width = param(shiftx, \B_WIDTH).as_int();
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if (param(shiftx, \B_SIGNED) != 0 && shiftxB[b_width-1] == RTLIL::S0)
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shiftxB = shiftxB.extract(0, b_width-1);
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if (port(macc, \Y) != shiftxB) {
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blacklist(shiftx);
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reject;
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}
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Const config = param(macc, \CONFIG);
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const int config_width = param(macc, \CONFIG_WIDTH).as_int();
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const int num_bits = config.extract(0, 4).as_int();
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const int num_ports = (config_width - 4) / (2 + 2*num_bits);
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if (num_ports != 1) {
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blacklist(shiftx);
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reject;
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}
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// IS_SIGNED?
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if (config[4] == 1) {
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blacklist(shiftx);
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reject;
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}
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// DO_SUBTRACT?
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if (config[5] == 1) {
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blacklist(shiftx);
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reject;
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}
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const int port_size_A = config.extract(6, num_bits).as_int();
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const int port_size_B = config.extract(6 + num_bits, num_bits).as_int();
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const SigSpec port_B = port(macc, \A).extract(port_size_A, port_size_B);
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if (!port_B.is_fully_const()) {
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blacklist(shiftx);
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reject;
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}
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const int multiply_factor = port_B.as_int();
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if (multiply_factor != param(shiftx, \Y_WIDTH).as_int()) {
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blacklist(shiftx);
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reject;
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}
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shiftxB = port(macc, \A).extract(0, port_size_A);
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}
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endcode
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