mirror of https://github.com/YosysHQ/yosys.git
Added additional options to BLIF backend
This commit is contained in:
parent
0ec5542ab4
commit
dc767d4e4c
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@ -29,14 +29,25 @@
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#include <string>
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#include <string>
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#include <assert.h>
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#include <assert.h>
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struct BlifDumperConfig
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{
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bool subckt_mode;
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bool conn_mode;
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bool impltf_mode;
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BlifDumperConfig() : subckt_mode(false), conn_mode(false), impltf_mode(false) { }
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};
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struct BlifDumper
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struct BlifDumper
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{
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{
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FILE *f;
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FILE *f;
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RTLIL::Module *module;
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RTLIL::Module *module;
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RTLIL::Design *design;
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RTLIL::Design *design;
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BlifDumperConfig *config;
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CellTypes ct;
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CellTypes ct;
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BlifDumper(FILE *f, RTLIL::Module *module, RTLIL::Design *design) : f(f), module(module), design(design), ct(design)
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BlifDumper(FILE *f, RTLIL::Module *module, RTLIL::Design *design, BlifDumperConfig *config) :
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f(f), module(module), design(design), config(config), ct(design)
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{
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{
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}
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}
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@ -103,51 +114,53 @@ struct BlifDumper
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}
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}
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fprintf(f, "\n");
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fprintf(f, "\n");
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fprintf(f, ".names $false\n");
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if (!config->impltf_mode) {
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fprintf(f, ".names $true\n1\n");
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fprintf(f, ".names $false\n");
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fprintf(f, ".names $true\n1\n");
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}
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for (auto &cell_it : module->cells)
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for (auto &cell_it : module->cells)
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{
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{
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RTLIL::Cell *cell = cell_it.second;
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RTLIL::Cell *cell = cell_it.second;
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if (cell->type == "$_INV_") {
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if (!config->subckt_mode && cell->type == "$_INV_") {
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fprintf(f, ".names %s %s\n0 1\n",
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fprintf(f, ".names %s %s\n0 1\n",
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cstr(cell->connections.at("\\A")), cstr(cell->connections.at("\\Y")));
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cstr(cell->connections.at("\\A")), cstr(cell->connections.at("\\Y")));
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continue;
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continue;
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}
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}
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if (cell->type == "$_AND_") {
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if (!config->subckt_mode && cell->type == "$_AND_") {
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fprintf(f, ".names %s %s %s\n11 1\n",
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fprintf(f, ".names %s %s %s\n11 1\n",
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cstr(cell->connections.at("\\A")), cstr(cell->connections.at("\\B")), cstr(cell->connections.at("\\Y")));
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cstr(cell->connections.at("\\A")), cstr(cell->connections.at("\\B")), cstr(cell->connections.at("\\Y")));
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continue;
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continue;
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}
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}
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if (cell->type == "$_OR_") {
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if (!config->subckt_mode && cell->type == "$_OR_") {
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fprintf(f, ".names %s %s %s\n1- 1\n-1 1\n",
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fprintf(f, ".names %s %s %s\n1- 1\n-1 1\n",
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cstr(cell->connections.at("\\A")), cstr(cell->connections.at("\\B")), cstr(cell->connections.at("\\Y")));
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cstr(cell->connections.at("\\A")), cstr(cell->connections.at("\\B")), cstr(cell->connections.at("\\Y")));
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continue;
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continue;
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}
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}
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if (cell->type == "$_XOR_") {
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if (!config->subckt_mode && cell->type == "$_XOR_") {
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fprintf(f, ".names %s %s %s\n10 1\n01 1\n",
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fprintf(f, ".names %s %s %s\n10 1\n01 1\n",
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cstr(cell->connections.at("\\A")), cstr(cell->connections.at("\\B")), cstr(cell->connections.at("\\Y")));
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cstr(cell->connections.at("\\A")), cstr(cell->connections.at("\\B")), cstr(cell->connections.at("\\Y")));
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continue;
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continue;
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}
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}
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if (cell->type == "$_MUX_") {
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if (!config->subckt_mode && cell->type == "$_MUX_") {
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fprintf(f, ".names %s %s %s %s\n1-0 1\n-11 1\n",
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fprintf(f, ".names %s %s %s %s\n1-0 1\n-11 1\n",
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cstr(cell->connections.at("\\A")), cstr(cell->connections.at("\\B")),
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cstr(cell->connections.at("\\A")), cstr(cell->connections.at("\\B")),
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cstr(cell->connections.at("\\S")), cstr(cell->connections.at("\\Y")));
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cstr(cell->connections.at("\\S")), cstr(cell->connections.at("\\Y")));
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continue;
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continue;
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}
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}
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if (cell->type == "$_DFF_N_") {
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if (!config->subckt_mode && cell->type == "$_DFF_N_") {
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fprintf(f, ".latch %s %s fe %s\n",
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fprintf(f, ".latch %s %s fe %s\n",
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cstr(cell->connections.at("\\D")), cstr(cell->connections.at("\\Q")), cstr(cell->connections.at("\\C")));
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cstr(cell->connections.at("\\D")), cstr(cell->connections.at("\\Q")), cstr(cell->connections.at("\\C")));
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continue;
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continue;
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}
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}
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if (cell->type == "$_DFF_P_") {
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if (!config->subckt_mode && cell->type == "$_DFF_P_") {
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fprintf(f, ".latch %s %s re %s\n",
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fprintf(f, ".latch %s %s re %s\n",
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cstr(cell->connections.at("\\D")), cstr(cell->connections.at("\\Q")), cstr(cell->connections.at("\\C")));
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cstr(cell->connections.at("\\D")), cstr(cell->connections.at("\\Q")), cstr(cell->connections.at("\\C")));
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continue;
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continue;
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@ -167,14 +180,17 @@ struct BlifDumper
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for (auto &conn : module->connections)
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for (auto &conn : module->connections)
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for (int i = 0; i < conn.first.width; i++)
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for (int i = 0; i < conn.first.width; i++)
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fprintf(f, ".names %s %s\n1 1\n", cstr(conn.second.extract(i, 1)), cstr(conn.first.extract(i, 1)));
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if (config->conn_mode)
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fprintf(f, ".conn %s %s\n", cstr(conn.second.extract(i, 1)), cstr(conn.first.extract(i, 1)));
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else
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fprintf(f, ".names %s %s\n1 1\n", cstr(conn.second.extract(i, 1)), cstr(conn.first.extract(i, 1)));
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fprintf(f, ".end\n");
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fprintf(f, ".end\n");
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}
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}
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static void dump(FILE *f, RTLIL::Module *module, RTLIL::Design *design)
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static void dump(FILE *f, RTLIL::Module *module, RTLIL::Design *design, BlifDumperConfig &config)
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{
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{
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BlifDumper dumper(f, module, design);
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BlifDumper dumper(f, module, design, &config);
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dumper.dump();
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dumper.dump();
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}
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}
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};
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};
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@ -192,10 +208,27 @@ struct BlifBackend : public Backend {
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log(" -top top_module\n");
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log(" -top top_module\n");
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log(" set the specified module as design top module\n");
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log(" set the specified module as design top module\n");
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log("\n");
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log("\n");
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log("\n");
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log("The following options can be usefull when the generated file is not going to be\n");
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log("read by a BLIF parser but a custom tool. It is recommended to not name the output\n");
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log("file *.blif when any of this options is used.\n");
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log("\n");
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log(" -subckt\n");
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log(" do not translate Yosys's internal gates to generic BLIF logic\n");
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log(" functions. Instead create .subckt lines for for all cells.\n");
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log("\n");
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log(" -conn\n");
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log(" do not generate buffers for connected wires. instead use the\n");
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log(" non-standard .conn statement.\n");
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log("\n");
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log(" -impltf\n");
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log(" do not write definitions for the $true and $false wires.\n");
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log("\n");
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}
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}
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virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
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virtual void execute(FILE *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design)
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{
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{
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std::string top_module_name;
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std::string top_module_name;
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BlifDumperConfig config;
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log_header("Executing BLIF backend.\n");
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log_header("Executing BLIF backend.\n");
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@ -206,6 +239,18 @@ struct BlifBackend : public Backend {
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top_module_name = args[++argidx];
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top_module_name = args[++argidx];
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continue;
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continue;
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}
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}
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if (args[argidx] == "-subckt") {
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config.subckt_mode = true;
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continue;
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}
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if (args[argidx] == "-conn") {
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config.conn_mode = true;
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continue;
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}
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if (args[argidx] == "-impltf") {
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config.impltf_mode = true;
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continue;
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}
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break;
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break;
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}
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}
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extra_args(f, filename, args, argidx);
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extra_args(f, filename, args, argidx);
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@ -224,7 +269,7 @@ struct BlifBackend : public Backend {
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log_error("Found munmapped emories in module %s: unmapped memories are not supported in BLIF backend!\n", RTLIL::id2cstr(module->name));
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log_error("Found munmapped emories in module %s: unmapped memories are not supported in BLIF backend!\n", RTLIL::id2cstr(module->name));
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if (module->name == RTLIL::escape_id(top_module_name)) {
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if (module->name == RTLIL::escape_id(top_module_name)) {
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BlifDumper::dump(f, module, design);
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BlifDumper::dump(f, module, design, config);
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top_module_name.clear();
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top_module_name.clear();
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continue;
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continue;
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}
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}
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@ -236,7 +281,7 @@ struct BlifBackend : public Backend {
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log_error("Can't find top module `%s'!\n", top_module_name.c_str());
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log_error("Can't find top module `%s'!\n", top_module_name.c_str());
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for (auto module : mod_list)
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for (auto module : mod_list)
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BlifDumper::dump(f, module, design);
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BlifDumper::dump(f, module, design, config);
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}
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}
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} BlifBackend;
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} BlifBackend;
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