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Simplify and fix for MACs

This commit is contained in:
Eddie Hung 2019-07-23 14:20:34 -07:00
parent 4f11ff8ebd
commit dc0c853abe
2 changed files with 38 additions and 56 deletions
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47
passes/pmgen/ice40_dsp.cc
View File

@ -81,25 +81,8 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
SigSpec B = st.sigB; SigSpec B = st.sigB;
B.extend_u0(16, b_signed); B.extend_u0(16, b_signed);
SigSpec CD; SigSpec CD = st.sigCD;
bool CD_signed = false; CD.extend_u0(32, st.sigCD_signed);
if (st.muxAB != st.addAB) {
if (st.muxA)
CD = st.muxA->getPort("\\B");
else if (st.muxB)
CD = st.muxB->getPort("\\A");
else log_abort();
CD_signed = a_signed && b_signed; // TODO: Do muxes have [AB]_SIGNED?
}
else if (st.addAB) {
if (st.addA)
CD = st.addAB->getPort("\\B");
else if (st.addB)
CD = st.addAB->getPort("\\A");
else log_abort();
CD_signed = st.sigO_signed;
}
CD.extend_u0(32, CD_signed);
cell->setPort("\\A", A); cell->setPort("\\A", A);
cell->setPort("\\B", B); cell->setPort("\\B", B);
@ -161,22 +144,14 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
// SB_MAC16 Output Interface // SB_MAC16 Output Interface
SigSpec O_lo = (st.ffO_lo ? st.sigO : (st.addAB ? st.addAB->getPort("\\Y") : st.sigH)).extract(0,16); cell->setPort("\\O", st.sigO);
if (GetSize(O_lo) < 16)
O_lo.append(pm.module->addWire(NEW_ID, 16-GetSize(O_lo)));
SigSpec O_hi = (st.ffO_hi ? st.sigO : (st.addAB ? st.addAB->getPort("\\Y") : st.sigH)).extract(16,16);
if (GetSize(O_hi) < 16)
O_hi.append(pm.module->addWire(NEW_ID, 16-GetSize(O_hi)));
SigSpec O{O_hi,O_lo};
cell->setPort("\\O", O);
bool accum = false; bool accum = false;
if (st.addAB) { if (st.addAB) {
if (st.addA) if (st.addA)
accum = (st.ffO_lo && st.ffO_hi && st.addAB->getPort("\\B") == O); accum = (st.ffO_lo && st.ffO_hi && st.addAB->getPort("\\B") == st.sigO);
else if (st.addB) else if (st.addB)
accum = (st.ffO_lo && st.ffO_hi && st.addAB->getPort("\\A") == O); accum = (st.ffO_lo && st.ffO_hi && st.addAB->getPort("\\A") == st.sigO);
else log_abort(); else log_abort();
if (accum) if (accum)
log(" accumulator %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type)); log(" accumulator %s (%s)\n", log_id(st.addAB), log_id(st.addAB->type));
@ -231,10 +206,14 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
pm.autoremove(st.mul); pm.autoremove(st.mul);
pm.autoremove(st.ffH); pm.autoremove(st.ffH);
pm.autoremove(st.addAB); pm.autoremove(st.addAB);
if (st.ffO_lo) if (st.ffO_lo) {
st.ffO_lo->connections_.at("\\Q").replace(O.extract(0,16), pm.module->addWire(NEW_ID, 16)); SigSpec O = st.sigO.extract(0,16);
if (st.ffO_hi) st.ffO_lo->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
st.ffO_hi->connections_.at("\\Q").replace(O.extract(16,16), pm.module->addWire(NEW_ID, 16)); }
if (st.ffO_hi) {
SigSpec O = st.sigO.extract(16,16);
st.ffO_hi->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
}
} }
struct Ice40DspPass : public Pass { struct Ice40DspPass : public Pass {

33
passes/pmgen/ice40_dsp.pmg
View File

@ -120,7 +120,6 @@ code addAB sigCD sigCD_signed sigO
endcode endcode
match muxA match muxA
if sigCD.empty()
select muxA->type.in($mux) select muxA->type.in($mux)
select nusers(port(muxA, \A)) == 2 select nusers(port(muxA, \A)) == 2
index <SigSpec> port(muxA, \A) === sigO index <SigSpec> port(muxA, \A) === sigO
@ -128,7 +127,6 @@ match muxA
endmatch endmatch
match muxB match muxB
if sigCD.empty()
if !muxA if !muxA
select muxB->type.in($mux) select muxB->type.in($mux)
select nusers(port(muxB, \B)) == 2 select nusers(port(muxB, \B)) == 2
@ -136,20 +134,11 @@ match muxB
optional optional
endmatch endmatch
code muxAB sigCD sigCD_signed sigO code muxAB
muxAB = addAB; if (muxA)
if (muxA) {
muxAB = muxA; muxAB = muxA;
sigCD = port(muxAB, \B); else if (muxB)
}
if (muxB) {
muxAB = muxB; muxAB = muxB;
sigCD = port(muxAB, \A);
}
if (muxA || muxB) {
sigO = port(muxAB, \Y);
sigCD_signed = addAB && param(addAB, \A_SIGNED).as_bool() && param(addAB, \B_SIGNED).as_bool();
}
endcode endcode
match ffO_lo match ffO_lo
@ -166,7 +155,7 @@ match ffO_hi
optional optional
endmatch endmatch
code clock clock_pol sigO code clock clock_pol sigO sigCD sigCD_signed
if (ffO_lo || ffO_hi) { if (ffO_lo || ffO_hi) {
if (ffO_lo) { if (ffO_lo) {
SigBit c = port(ffO_lo, \CLK).as_bit(); SigBit c = port(ffO_lo, \CLK).as_bit();
@ -195,5 +184,19 @@ code clock clock_pol sigO
if (port(ffO_hi, \Q) != sigO.extract(16,16)) if (port(ffO_hi, \Q) != sigO.extract(16,16))
sigO.replace(port(ffO_hi, \D), port(ffO_hi, \Q)); sigO.replace(port(ffO_hi, \D), port(ffO_hi, \Q));
} }
// Loading value into output register is not
// supported unless using accumulator
if (muxAB && sigCD != sigO) {
if (muxAB != addAB)
reject;
if (muxA)
sigCD = port(muxAB, \B);
else if (muxB)
sigCD = port(muxAB, \A);
else log_abort();
sigCD_signed = addAB && param(addAB, \A_SIGNED).as_bool() && param(addAB, \B_SIGNED).as_bool();
}
} }
endcode endcode