From dbf1d037e806e925db6ba249432cc90dd64605a1 Mon Sep 17 00:00:00 2001
From: Miodrag Milanovic <mmicko@gmail.com>
Date: Wed, 24 Jul 2024 13:41:12 +0200
Subject: [PATCH] Cleanup

---
 techlibs/nanoxplore/brams_map.v   |  2 +-
 techlibs/nanoxplore/cells_bb.v    | 92 -------------------------------
 techlibs/nanoxplore/cells_sim_u.v | 30 +++++-----
 tests/arch/nanoxplore/add_sub.ys  |  2 +-
 4 files changed, 17 insertions(+), 109 deletions(-)

diff --git a/techlibs/nanoxplore/brams_map.v b/techlibs/nanoxplore/brams_map.v
index 4609eee84..506e2dd0b 100644
--- a/techlibs/nanoxplore/brams_map.v
+++ b/techlibs/nanoxplore/brams_map.v
@@ -81,4 +81,4 @@ NX_RAM_WRAP #(
     .BI(B_DATA),
     .BO(PORT_B_RD_DATA)
 );
-endmodule
\ No newline at end of file
+endmodule
diff --git a/techlibs/nanoxplore/cells_bb.v b/techlibs/nanoxplore/cells_bb.v
index 1e98a6f3b..919a02f82 100644
--- a/techlibs/nanoxplore/cells_bb.v
+++ b/techlibs/nanoxplore/cells_bb.v
@@ -1,95 +1,3 @@
-//(* blackbox *)
-//module NX_LUT(I1, I2, I3, I4, O);
-//    input I1;
-//    input I2;
-//    input I3;
-//    input I4;
-//    output O;
-//    parameter lut_table = 16'b0000000000000000;
-//endmodule
-
-//(* blackbox *)
-//module NX_CY(A1, A2, A3, A4, B1, B2, B3, B4, CI, CO, S1, S2, S3, S4);
-//    input A1;
-//    input A2;
-//    input A3;
-//    input A4;
-//    input B1;
-//    input B2;
-//    input B3;
-//    input B4;
-//    input CI;
-//    output CO;
-//    output S1;
-//    output S2;
-//    output S3;
-//    output S4;
-//    parameter add_carry = 0;
-//endmodule
-
-// Bypass mode of NX_GCK_U
-//(* blackbox *)
-//module NX_BD(I, O);
-//    input I;
-//    output O;
-//    parameter mode = "global_lowskew";
-//endmodule
-
-//(* blackbox *)
-//module NX_DFF(I, CK, L, R, O);
-//    input CK;
-//    input I;
-//    input L;
-//    output O;
-//    input R;
-//    parameter dff_ctxt = 1'b0;
-//    parameter dff_edge = 1'b0;
-//    parameter dff_init = 1'b0;
-//    parameter dff_load = 1'b0;
-//    parameter dff_sync = 1'b0;
-//    parameter dff_type = 1'b0;
-//endmodule
-
-// Special mode of NX_DFF
-//(* blackbox *)
-//module NX_BFF(I, O);
-//    input I;
-//    output O;
-//endmodule
-
-// (* blackbox *)
-// module NX_DFR(I, CK, L, R, O);
-//     input CK;
-//     input I;
-//     input L;
-//     output O;
-//     input R;
-//     parameter data_inv = 1'b0;
-//     parameter dff_edge = 1'b0;
-//     parameter dff_init = 1'b0;
-//     parameter dff_load = 1'b0;
-//     parameter dff_sync = 1'b0;
-//     parameter dff_type = 1'b0;
-//     parameter iobname = "";
-//     parameter location = "";
-//     parameter mode = 0;
-//     parameter path = 0;
-//     parameter ring = 0;
-// endmodule
-
-// Special mode of NX_DFR
-//(* blackbox *)
-//module NX_BFR(I, O);
-//    input I;
-//    output O;
-//    parameter data_inv = 1'b0;
-//    parameter iobname = "";
-//    parameter location = "";
-//    parameter mode = 0;
-//    parameter path = 0;
-//    parameter ring = 0;
-//endmodule
-
 // NX_RAM related
 (* blackbox *)
 module NX_ECC(CKD, CHK, COR, ERR);
diff --git a/techlibs/nanoxplore/cells_sim_u.v b/techlibs/nanoxplore/cells_sim_u.v
index 0456a4691..e11aaabee 100644
--- a/techlibs/nanoxplore/cells_sim_u.v
+++ b/techlibs/nanoxplore/cells_sim_u.v
@@ -12,20 +12,21 @@ module NX_GCK_U(SI1, SI2, CMD, SO);
     wire SI2_int = inv_in ? ~SI2 : SI2;
 
     wire SO_int;
-    generate if (std_mode == "BYPASS") begin
-        assign SO_int = SI1_int;
-    end
-    else if (std_mode == "MUX") begin
-        assign SO_int = CMD ? SI1_int : SI2_int;
-    end
-    else if (std_mode == "CKS") begin
-        assign SO_int = CMD ? SI1_int : 1'b0;
-    end
-    else if (std_mode == "CSC") begin
-        assign SO_int = CMD;
-    end
-    else
-    $error("Unrecognised std_mode");
+    generate
+        if (std_mode == "BYPASS") begin
+            assign SO_int = SI1_int;
+        end
+        else if (std_mode == "MUX") begin
+            assign SO_int = CMD ? SI1_int : SI2_int;
+        end
+        else if (std_mode == "CKS") begin
+            assign SO_int = CMD ? SI1_int : 1'b0;
+        end
+        else if (std_mode == "CSC") begin
+            assign SO_int = CMD;
+        end
+        else
+            $error("Unrecognised std_mode");
     endgenerate
     assign SO = inv_out ? ~SO_int : SO_int;
 endmodule
@@ -302,5 +303,4 @@ module NX_DDFR_U(CK,CKF,R,I,I2,L,O,O2);
         else
             $error("Unknown NX_DDFR_U path");
     endgenerate
-
 endmodule
diff --git a/tests/arch/nanoxplore/add_sub.ys b/tests/arch/nanoxplore/add_sub.ys
index f7895ac5b..9356944c8 100644
--- a/tests/arch/nanoxplore/add_sub.ys
+++ b/tests/arch/nanoxplore/add_sub.ys
@@ -68,4 +68,4 @@ design -load postopt
 cd top
 stat
 select -assert-count 48 t:NX_CY
-select -assert-none t:NX_CY %% t:* %D
\ No newline at end of file
+select -assert-none t:NX_CY %% t:* %D