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Tidy up ice40_dsp some more

This commit is contained in:
Eddie Hung 2019-09-06 12:16:40 -07:00
parent 776d769941
commit da8fe83f7a
2 changed files with 13 additions and 14 deletions
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6
passes/pmgen/ice40_dsp.cc
View File

@ -219,10 +219,10 @@ void create_ice40_dsp(ice40_dsp_pm &pm)
cell->setParam("\\B_SIGNED", st.mul->getParam("\\B_SIGNED").as_bool()); cell->setParam("\\B_SIGNED", st.mul->getParam("\\B_SIGNED").as_bool());
if (st.ffO) { if (st.ffO) {
if (st.ffO_hilo) if (st.ffO_lo)
cell->setParam("\\TOPOUTPUT_SELECT", Const(1, 2));
else
cell->setParam("\\TOPOUTPUT_SELECT", Const(st.addAB ? 0 : 3, 2)); cell->setParam("\\TOPOUTPUT_SELECT", Const(st.addAB ? 0 : 3, 2));
else
cell->setParam("\\TOPOUTPUT_SELECT", Const(1, 2));
st.ffO->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O))); st.ffO->connections_.at("\\Q").replace(O, pm.module->addWire(NEW_ID, GetSize(O)));
cell->setParam("\\BOTOUTPUT_SELECT", Const(1, 2)); cell->setParam("\\BOTOUTPUT_SELECT", Const(1, 2));

21
passes/pmgen/ice40_dsp.pmg
View File

@ -3,7 +3,7 @@ pattern ice40_dsp
state <SigBit> clock state <SigBit> clock
state <bool> clock_pol cd_signed state <bool> clock_pol cd_signed
state <SigSpec> sigA sigB sigCD sigH sigO state <SigSpec> sigA sigB sigCD sigH sigO
state <Cell*> addAB muxAB ffO state <Cell*> addAB muxAB
match mul match mul
select mul->type.in($mul, \SB_MAC16) select mul->type.in($mul, \SB_MAC16)
@ -202,21 +202,21 @@ code muxAB sigO
sigO = port(muxAB, \Y); sigO = port(muxAB, \Y);
endcode endcode
match ffO_hilo match ffO
// Ensure that register is not already used // Ensure that register is not already used
if mul->type != \SB_MAC16 || (mul->parameters.at(\TOPOUTPUT_SELECT, 0).as_int() != 1 && mul->parameters.at(\BOTOUTPUT_SELECT, 0).as_int() != 1) if mul->type != \SB_MAC16 || (mul->parameters.at(\TOPOUTPUT_SELECT, 0).as_int() != 1 && mul->parameters.at(\BOTOUTPUT_SELECT, 0).as_int() != 1)
// Ensure that OLOADTOP/OLOADBOT is unused or zero // Ensure that OLOADTOP/OLOADBOT is unused or zero
if mul->type != \SB_MAC16 || (mul->connections_.at(\OLOADTOP, State::S0).is_fully_zero() && mul->connections_.at(\OLOADBOT, State::S0).is_fully_zero()) if mul->type != \SB_MAC16 || (mul->connections_.at(\OLOADTOP, State::S0).is_fully_zero() && mul->connections_.at(\OLOADBOT, State::S0).is_fully_zero())
if nusers(sigO) == 2 if nusers(sigO) == 2
select ffO_hilo->type.in($dff) select ffO->type.in($dff)
filter GetSize(port(ffO_hilo, \D)) >= GetSize(sigO) filter GetSize(port(ffO, \D)) >= GetSize(sigO)
slice offset GetSize(port(ffO_hilo, \D)) slice offset GetSize(port(ffO, \D))
filter offset+GetSize(sigO) <= GetSize(port(ffO_hilo, \D)) && port(ffO_hilo, \D).extract(offset, GetSize(sigO)) == sigO filter offset+GetSize(sigO) <= GetSize(port(ffO, \D)) && port(ffO, \D).extract(offset, GetSize(sigO)) == sigO
optional optional
endmatch endmatch
match ffO_lo match ffO_lo
if !ffO_hilo && GetSize(sigO) > 16 if !ffO && GetSize(sigO) > 16
// Ensure that register is not already used // Ensure that register is not already used
if mul->type != \SB_MAC16 || (mul->parameters.at(\TOPOUTPUT_SELECT, 0).as_int() != 1 && mul->parameters.at(\BOTOUTPUT_SELECT, 0).as_int() != 1) if mul->type != \SB_MAC16 || (mul->parameters.at(\TOPOUTPUT_SELECT, 0).as_int() != 1 && mul->parameters.at(\BOTOUTPUT_SELECT, 0).as_int() != 1)
// Ensure that OLOADTOP/OLOADBOT is unused or zero // Ensure that OLOADTOP/OLOADBOT is unused or zero
@ -230,11 +230,10 @@ match ffO_lo
endmatch endmatch
code ffO clock clock_pol sigO sigCD cd_signed code ffO clock clock_pol sigO sigCD cd_signed
ffO = nullptr; if (ffO_lo) {
if (ffO_hilo) log_assert(!ffO);
ffO = ffO_hilo;
else if (ffO_lo)
ffO = ffO_lo; ffO = ffO_lo;
}
if (ffO) { if (ffO) {
for (auto b : port(ffO, \Q)) for (auto b : port(ffO, \Q))
if (b.wire->get_bool_attribute(\keep)) if (b.wire->get_bool_attribute(\keep))