mirror of https://github.com/YosysHQ/yosys.git
Merge pull request #1098 from YosysHQ/xaig
"abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
This commit is contained in:
Eddie Hung
GitHub
commit
da5f830395
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@ -23,6 +23,11 @@ Yosys 0.8 .. Yosys 0.8-dev
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- Added "muxcover -nopartial"
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- Added "muxpack" pass
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- Added "pmux2shiftx -norange"
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- Added "write_xaiger" backend
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- Added "abc9" pass for timing-aware techmapping (experimental, FPGA only, no FFs)
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- Added "synth_xilinx -abc9" (experimental)
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- Added "synth_ice40 -abc9" (experimental)
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- Added "synth -abc9" (experimental)
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- "synth_xilinx" to now infer hard shift registers (-nosrl to disable)
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- Fixed sign extension of unsized constants with 'bx and 'bz MSB
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3
Makefile
3
Makefile
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@ -122,7 +122,7 @@ OBJS = kernel/version_$(GIT_REV).o
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# is just a symlink to your actual ABC working directory, as 'make mrproper'
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# will remove the 'abc' directory and you do not want to accidentally
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# delete your work on ABC..
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ABCREV = 3709744
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ABCREV = 62487de
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ABCPULL = 1
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ABCURL ?= https://github.com/berkeley-abc/abc
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ABCMKARGS = CC="$(CXX)" CXX="$(CXX)" ABC_USE_LIBSTDCXX=1
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@ -688,6 +688,7 @@ test: $(TARGETS) $(EXTRA_TARGETS)
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+cd tests/opt && bash run-test.sh
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+cd tests/aiger && bash run-test.sh $(ABCOPT)
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+cd tests/arch && bash run-test.sh
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+cd tests/simple_abc9 && bash run-test.sh $(SEEDOPT)
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@echo ""
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@echo " Passed \"make test\"."
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@echo ""
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@ -1,3 +1,4 @@
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OBJS += backends/aiger/aiger.o
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OBJS += backends/aiger/xaiger.o
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@ -70,35 +70,35 @@ struct AigerWriter
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int bit2aig(SigBit bit)
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{
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if (aig_map.count(bit) == 0)
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{
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aig_map[bit] = -1;
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if (initstate_bits.count(bit)) {
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log_assert(initstate_ff > 0);
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aig_map[bit] = initstate_ff;
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} else
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if (not_map.count(bit)) {
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int a = bit2aig(not_map.at(bit)) ^ 1;
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aig_map[bit] = a;
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} else
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if (and_map.count(bit)) {
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auto args = and_map.at(bit);
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int a0 = bit2aig(args.first);
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int a1 = bit2aig(args.second);
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aig_map[bit] = mkgate(a0, a1);
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} else
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if (alias_map.count(bit)) {
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int a = bit2aig(alias_map.at(bit));
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aig_map[bit] = a;
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}
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if (bit == State::Sx || bit == State::Sz)
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log_error("Design contains 'x' or 'z' bits. Use 'setundef' to replace those constants.\n");
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auto it = aig_map.find(bit);
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if (it != aig_map.end()) {
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log_assert(it->second >= 0);
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return it->second;
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}
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log_assert(aig_map.at(bit) >= 0);
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return aig_map.at(bit);
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// NB: Cannot use iterator returned from aig_map.insert()
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// since this function is called recursively
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int a = -1;
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if (not_map.count(bit)) {
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a = bit2aig(not_map.at(bit)) ^ 1;
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} else
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if (and_map.count(bit)) {
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auto args = and_map.at(bit);
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int a0 = bit2aig(args.first);
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int a1 = bit2aig(args.second);
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a = mkgate(a0, a1);
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} else
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if (alias_map.count(bit)) {
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a = bit2aig(alias_map.at(bit));
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}
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if (bit == State::Sx || bit == State::Sz)
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log_error("Design contains 'x' or 'z' bits. Use 'setundef' to replace those constants.\n");
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log_assert(a >= 0);
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aig_map[bit] = a;
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return a;
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}
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AigerWriter(Module *module, bool zinit_mode, bool imode, bool omode, bool bmode) : module(module), zinit_mode(zinit_mode), sigmap(module)
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@ -686,7 +686,7 @@ struct AigerBackend : public Backend {
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log("invariant constraints.\n");
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log("\n");
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log(" -ascii\n");
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log(" write ASCII version of AGIER format\n");
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log(" write ASCII version of AIGER format\n");
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log("\n");
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log(" -zinit\n");
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log(" convert FFs to zero-initialized FFs, adding additional inputs for\n");
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@ -0,0 +1,868 @@
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/*
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* yosys -- Yosys Open SYnthesis Suite
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*
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* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
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* 2019 Eddie Hung <eddie@fpgeh.com>
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*
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* Permission to use, copy, modify, and/or distribute this software for any
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* purpose with or without fee is hereby granted, provided that the above
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* copyright notice and this permission notice appear in all copies.
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*
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* THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
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* WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
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* MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
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* ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
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* WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
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* ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
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* OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
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*
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*/
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// https://stackoverflow.com/a/46137633
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#ifdef _MSC_VER
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#include <stdlib.h>
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#define __builtin_bswap32 _byteswap_ulong
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#elif defined(__APPLE__)
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#include <libkern/OSByteOrder.h>
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#define __builtin_bswap32 OSSwapInt32
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#elif !defined(__GNUC__)
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#include <cstdint>
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inline uint32_t __builtin_bswap32(uint32_t x)
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{
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// https://stackoverflow.com/a/27796212
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register uint32_t value = number_to_be_reversed;
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uint8_t lolo = (value >> 0) & 0xFF;
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uint8_t lohi = (value >> 8) & 0xFF;
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uint8_t hilo = (value >> 16) & 0xFF;
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uint8_t hihi = (value >> 24) & 0xFF;
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return (hihi << 24)
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| (hilo << 16)
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| (lohi << 8)
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| (lolo << 0);
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}
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#endif
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#include "kernel/yosys.h"
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#include "kernel/sigtools.h"
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#include "kernel/utils.h"
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USING_YOSYS_NAMESPACE
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PRIVATE_NAMESPACE_BEGIN
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inline int32_t to_big_endian(int32_t i32) {
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#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
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return __builtin_bswap32(i32);
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#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
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return i32;
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#else
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#error "Unknown endianness"
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#endif
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}
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void aiger_encode(std::ostream &f, int x)
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{
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log_assert(x >= 0);
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while (x & ~0x7f) {
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f.put((x & 0x7f) | 0x80);
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x = x >> 7;
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}
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f.put(x);
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}
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struct XAigerWriter
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{
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Module *module;
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SigMap sigmap;
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pool<SigBit> input_bits, output_bits;
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dict<SigBit, SigBit> not_map, alias_map;
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dict<SigBit, pair<SigBit, SigBit>> and_map;
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vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int>> ci_bits;
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vector<std::tuple<SigBit,RTLIL::Cell*,RTLIL::IdString,int,int>> co_bits;
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vector<pair<int, int>> aig_gates;
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vector<int> aig_outputs;
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int aig_m = 0, aig_i = 0, aig_l = 0, aig_o = 0, aig_a = 0;
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dict<SigBit, int> aig_map;
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dict<SigBit, int> ordered_outputs;
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vector<Cell*> box_list;
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bool omode = false;
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int mkgate(int a0, int a1)
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{
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aig_m++, aig_a++;
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aig_gates.push_back(a0 > a1 ? make_pair(a0, a1) : make_pair(a1, a0));
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return 2*aig_m;
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}
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int bit2aig(SigBit bit)
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{
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auto it = aig_map.find(bit);
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if (it != aig_map.end()) {
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log_assert(it->second >= 0);
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return it->second;
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}
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// NB: Cannot use iterator returned from aig_map.insert()
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// since this function is called recursively
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int a = -1;
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if (not_map.count(bit)) {
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a = bit2aig(not_map.at(bit)) ^ 1;
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} else
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if (and_map.count(bit)) {
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auto args = and_map.at(bit);
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int a0 = bit2aig(args.first);
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int a1 = bit2aig(args.second);
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a = mkgate(a0, a1);
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} else
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if (alias_map.count(bit)) {
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a = bit2aig(alias_map.at(bit));
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}
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if (bit == State::Sx || bit == State::Sz) {
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log_debug("Design contains 'x' or 'z' bits. Treating as 1'b0.\n");
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a = aig_map.at(State::S0);
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}
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log_assert(a >= 0);
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aig_map[bit] = a;
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return a;
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}
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XAigerWriter(Module *module, bool holes_mode=false) : module(module), sigmap(module)
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{
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pool<SigBit> undriven_bits;
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pool<SigBit> unused_bits;
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// promote public wires
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for (auto wire : module->wires())
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if (wire->name[0] == '\\')
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sigmap.add(wire);
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// promote input wires
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for (auto wire : module->wires())
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if (wire->port_input)
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sigmap.add(wire);
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// promote output wires
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for (auto wire : module->wires())
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if (wire->port_output)
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sigmap.add(wire);
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for (auto wire : module->wires())
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{
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bool keep = wire->attributes.count("\\keep");
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for (int i = 0; i < GetSize(wire); i++)
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{
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SigBit wirebit(wire, i);
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SigBit bit = sigmap(wirebit);
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if (bit.wire) {
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undriven_bits.insert(bit);
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unused_bits.insert(bit);
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}
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if (wire->port_input || keep) {
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if (bit != wirebit)
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alias_map[bit] = wirebit;
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input_bits.insert(wirebit);
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}
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if (wire->port_output || keep) {
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if (bit != RTLIL::Sx) {
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if (bit != wirebit)
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alias_map[wirebit] = bit;
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output_bits.insert(wirebit);
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}
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else
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log_debug("Skipping PO '%s' driven by 1'bx\n", log_signal(wirebit));
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}
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}
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}
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for (auto bit : input_bits)
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undriven_bits.erase(sigmap(bit));
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for (auto bit : output_bits)
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if (!bit.wire->port_input)
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unused_bits.erase(bit);
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// TODO: Speed up toposort -- ultimately we care about
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// box ordering, but not individual AIG cells
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dict<SigBit, pool<IdString>> bit_drivers, bit_users;
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TopoSort<IdString, RTLIL::sort_by_id_str> toposort;
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bool abc_box_seen = false;
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for (auto cell : module->selected_cells()) {
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if (cell->type == "$_NOT_")
|
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{
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SigBit A = sigmap(cell->getPort("\\A").as_bit());
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SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
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unused_bits.erase(A);
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undriven_bits.erase(Y);
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not_map[Y] = A;
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if (!holes_mode) {
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toposort.node(cell->name);
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bit_users[A].insert(cell->name);
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bit_drivers[Y].insert(cell->name);
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}
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continue;
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}
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if (cell->type == "$_AND_")
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{
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SigBit A = sigmap(cell->getPort("\\A").as_bit());
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SigBit B = sigmap(cell->getPort("\\B").as_bit());
|
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SigBit Y = sigmap(cell->getPort("\\Y").as_bit());
|
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unused_bits.erase(A);
|
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unused_bits.erase(B);
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undriven_bits.erase(Y);
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and_map[Y] = make_pair(A, B);
|
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if (!holes_mode) {
|
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toposort.node(cell->name);
|
||||
bit_users[A].insert(cell->name);
|
||||
bit_users[B].insert(cell->name);
|
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bit_drivers[Y].insert(cell->name);
|
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}
|
||||
continue;
|
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}
|
||||
|
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log_assert(!holes_mode);
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|
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RTLIL::Module* inst_module = module->design->module(cell->type);
|
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if (inst_module && inst_module->attributes.count("\\abc_box_id")) {
|
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abc_box_seen = true;
|
||||
|
||||
if (!holes_mode) {
|
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toposort.node(cell->name);
|
||||
for (const auto &conn : cell->connections()) {
|
||||
if (cell->input(conn.first)) {
|
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// Ignore inout for the sake of topographical ordering
|
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if (cell->output(conn.first)) continue;
|
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for (auto bit : sigmap(conn.second))
|
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bit_users[bit].insert(cell->name);
|
||||
}
|
||||
|
||||
if (cell->output(conn.first))
|
||||
for (auto bit : sigmap(conn.second))
|
||||
bit_drivers[bit].insert(cell->name);
|
||||
}
|
||||
}
|
||||
}
|
||||
else {
|
||||
for (const auto &c : cell->connections()) {
|
||||
if (c.second.is_fully_const()) continue;
|
||||
auto is_input = cell->input(c.first);
|
||||
auto is_output = cell->output(c.first);
|
||||
if (!is_input && !is_output)
|
||||
log_error("Connection '%s' on cell '%s' (type '%s') not recognised!\n", log_id(c.first), log_id(cell), log_id(cell->type));
|
||||
|
||||
if (is_input) {
|
||||
for (auto b : c.second.bits()) {
|
||||
Wire *w = b.wire;
|
||||
if (!w) continue;
|
||||
if (!w->port_output) {
|
||||
SigBit I = sigmap(b);
|
||||
if (I != b)
|
||||
alias_map[b] = I;
|
||||
output_bits.insert(b);
|
||||
unused_bits.erase(b);
|
||||
}
|
||||
}
|
||||
}
|
||||
if (is_output) {
|
||||
for (auto b : c.second.bits()) {
|
||||
Wire *w = b.wire;
|
||||
if (!w) continue;
|
||||
input_bits.insert(b);
|
||||
SigBit O = sigmap(b);
|
||||
if (O != b)
|
||||
alias_map[O] = b;
|
||||
undriven_bits.erase(O);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
//log_warning("Unsupported cell type: %s (%s)\n", log_id(cell->type), log_id(cell));
|
||||
}
|
||||
|
||||
if (abc_box_seen) {
|
||||
for (auto &it : bit_users)
|
||||
if (bit_drivers.count(it.first))
|
||||
for (auto driver_cell : bit_drivers.at(it.first))
|
||||
for (auto user_cell : it.second)
|
||||
toposort.edge(driver_cell, user_cell);
|
||||
|
||||
#if 0
|
||||
toposort.analyze_loops = true;
|
||||
#endif
|
||||
bool no_loops = toposort.sort();
|
||||
#if 0
|
||||
unsigned i = 0;
|
||||
for (auto &it : toposort.loops) {
|
||||
log(" loop %d\n", i++);
|
||||
for (auto cell_name : it) {
|
||||
auto cell = module->cell(cell_name);
|
||||
log_assert(cell);
|
||||
log("\t%s (%s @ %s)\n", log_id(cell), log_id(cell->type), cell->get_src_attribute().c_str());
|
||||
}
|
||||
}
|
||||
#endif
|
||||
log_assert(no_loops);
|
||||
|
||||
pool<IdString> seen_boxes;
|
||||
for (auto cell_name : toposort.sorted) {
|
||||
RTLIL::Cell *cell = module->cell(cell_name);
|
||||
log_assert(cell);
|
||||
|
||||
RTLIL::Module* box_module = module->design->module(cell->type);
|
||||
if (!box_module || !box_module->attributes.count("\\abc_box_id"))
|
||||
continue;
|
||||
|
||||
if (seen_boxes.insert(cell->type).second) {
|
||||
auto it = box_module->attributes.find("\\abc_carry");
|
||||
if (it != box_module->attributes.end()) {
|
||||
RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr;
|
||||
auto carry_in_out = it->second.decode_string();
|
||||
auto pos = carry_in_out.find(',');
|
||||
if (pos == std::string::npos)
|
||||
log_error("'abc_carry' attribute on module '%s' does not contain ','.\n", log_id(cell->type));
|
||||
auto carry_in_name = RTLIL::escape_id(carry_in_out.substr(0, pos));
|
||||
carry_in = box_module->wire(carry_in_name);
|
||||
if (!carry_in || !carry_in->port_input)
|
||||
log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an input port.\n", log_id(cell->type), carry_in_name.c_str());
|
||||
|
||||
auto carry_out_name = RTLIL::escape_id(carry_in_out.substr(pos+1));
|
||||
carry_out = box_module->wire(carry_out_name);
|
||||
if (!carry_out || !carry_out->port_output)
|
||||
log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an output port.\n", log_id(cell->type), carry_out_name.c_str());
|
||||
|
||||
auto &ports = box_module->ports;
|
||||
for (auto jt = ports.begin(); jt != ports.end(); ) {
|
||||
RTLIL::Wire* w = box_module->wire(*jt);
|
||||
log_assert(w);
|
||||
if (w == carry_in || w == carry_out) {
|
||||
jt = ports.erase(jt);
|
||||
continue;
|
||||
}
|
||||
if (w->port_id > carry_in->port_id)
|
||||
--w->port_id;
|
||||
if (w->port_id > carry_out->port_id)
|
||||
--w->port_id;
|
||||
log_assert(w->port_input || w->port_output);
|
||||
log_assert(ports[w->port_id-1] == w->name);
|
||||
++jt;
|
||||
}
|
||||
ports.push_back(carry_in->name);
|
||||
carry_in->port_id = ports.size();
|
||||
ports.push_back(carry_out->name);
|
||||
carry_out->port_id = ports.size();
|
||||
}
|
||||
}
|
||||
|
||||
// Fully pad all unused input connections of this box cell with S0
|
||||
// Fully pad all undriven output connections of this box cell with anonymous wires
|
||||
// NB: Assume box_module->ports are sorted alphabetically
|
||||
// (as RTLIL::Module::fixup_ports() would do)
|
||||
for (const auto &port_name : box_module->ports) {
|
||||
RTLIL::Wire* w = box_module->wire(port_name);
|
||||
log_assert(w);
|
||||
auto it = cell->connections_.find(port_name);
|
||||
if (w->port_input) {
|
||||
RTLIL::SigSpec rhs;
|
||||
if (it != cell->connections_.end()) {
|
||||
if (GetSize(it->second) < GetSize(w))
|
||||
it->second.append(RTLIL::SigSpec(RTLIL::S0, GetSize(w)-GetSize(it->second)));
|
||||
rhs = it->second;
|
||||
}
|
||||
else {
|
||||
rhs = RTLIL::SigSpec(RTLIL::S0, GetSize(w));
|
||||
cell->setPort(port_name, rhs);
|
||||
}
|
||||
|
||||
int offset = 0;
|
||||
for (auto b : rhs.bits()) {
|
||||
SigBit I = sigmap(b);
|
||||
if (b == RTLIL::Sx)
|
||||
b = RTLIL::S0;
|
||||
else if (I != b) {
|
||||
if (I == RTLIL::Sx)
|
||||
alias_map[b] = RTLIL::S0;
|
||||
else
|
||||
alias_map[b] = I;
|
||||
}
|
||||
co_bits.emplace_back(b, cell, port_name, offset++, 0);
|
||||
unused_bits.erase(b);
|
||||
}
|
||||
}
|
||||
if (w->port_output) {
|
||||
RTLIL::SigSpec rhs;
|
||||
auto it = cell->connections_.find(w->name);
|
||||
if (it != cell->connections_.end()) {
|
||||
if (GetSize(it->second) < GetSize(w))
|
||||
it->second.append(module->addWire(NEW_ID, GetSize(w)-GetSize(it->second)));
|
||||
rhs = it->second;
|
||||
}
|
||||
else {
|
||||
rhs = module->addWire(NEW_ID, GetSize(w));
|
||||
cell->setPort(port_name, rhs);
|
||||
}
|
||||
|
||||
int offset = 0;
|
||||
for (const auto &b : rhs.bits()) {
|
||||
ci_bits.emplace_back(b, cell, port_name, offset++);
|
||||
SigBit O = sigmap(b);
|
||||
if (O != b)
|
||||
alias_map[O] = b;
|
||||
undriven_bits.erase(O);
|
||||
|
||||
auto jt = input_bits.find(b);
|
||||
if (jt != input_bits.end()) {
|
||||
log_assert(b.wire->attributes.count("\\keep"));
|
||||
input_bits.erase(b);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
box_list.emplace_back(cell);
|
||||
}
|
||||
|
||||
// TODO: Free memory from toposort, bit_drivers, bit_users
|
||||
}
|
||||
|
||||
for (auto bit : input_bits) {
|
||||
if (!output_bits.count(bit))
|
||||
continue;
|
||||
RTLIL::Wire *wire = bit.wire;
|
||||
// If encountering an inout port, or a keep-ed wire, then create a new wire
|
||||
// with $inout.out suffix, make it a PO driven by the existing inout, and
|
||||
// inherit existing inout's drivers
|
||||
if ((wire->port_input && wire->port_output && !undriven_bits.count(bit))
|
||||
|| wire->attributes.count("\\keep")) {
|
||||
RTLIL::IdString wire_name = wire->name.str() + "$inout.out";
|
||||
RTLIL::Wire *new_wire = module->wire(wire_name);
|
||||
if (!new_wire)
|
||||
new_wire = module->addWire(wire_name, GetSize(wire));
|
||||
SigBit new_bit(new_wire, bit.offset);
|
||||
module->connect(new_bit, bit);
|
||||
if (not_map.count(bit)) {
|
||||
auto a = not_map.at(bit);
|
||||
not_map[new_bit] = a;
|
||||
}
|
||||
else if (and_map.count(bit)) {
|
||||
auto a = and_map.at(bit);
|
||||
and_map[new_bit] = a;
|
||||
}
|
||||
else if (alias_map.count(bit)) {
|
||||
auto a = alias_map.at(bit);
|
||||
alias_map[new_bit] = a;
|
||||
}
|
||||
else
|
||||
alias_map[new_bit] = bit;
|
||||
output_bits.erase(bit);
|
||||
output_bits.insert(new_bit);
|
||||
}
|
||||
}
|
||||
|
||||
for (auto bit : unused_bits)
|
||||
undriven_bits.erase(bit);
|
||||
|
||||
if (!undriven_bits.empty() && !holes_mode) {
|
||||
undriven_bits.sort();
|
||||
for (auto bit : undriven_bits) {
|
||||
log_warning("Treating undriven bit %s.%s like $anyseq.\n", log_id(module), log_signal(bit));
|
||||
input_bits.insert(bit);
|
||||
}
|
||||
log_warning("Treating a total of %d undriven bits in %s like $anyseq.\n", GetSize(undriven_bits), log_id(module));
|
||||
}
|
||||
|
||||
if (holes_mode) {
|
||||
struct sort_by_port_id {
|
||||
bool operator()(const RTLIL::SigBit& a, const RTLIL::SigBit& b) const {
|
||||
return a.wire->port_id < b.wire->port_id;
|
||||
}
|
||||
};
|
||||
input_bits.sort(sort_by_port_id());
|
||||
output_bits.sort(sort_by_port_id());
|
||||
}
|
||||
else {
|
||||
input_bits.sort();
|
||||
output_bits.sort();
|
||||
}
|
||||
|
||||
not_map.sort();
|
||||
and_map.sort();
|
||||
|
||||
aig_map[State::S0] = 0;
|
||||
aig_map[State::S1] = 1;
|
||||
|
||||
for (auto bit : input_bits) {
|
||||
aig_m++, aig_i++;
|
||||
log_assert(!aig_map.count(bit));
|
||||
aig_map[bit] = 2*aig_m;
|
||||
}
|
||||
|
||||
for (auto &c : ci_bits) {
|
||||
RTLIL::SigBit bit = std::get<0>(c);
|
||||
aig_m++, aig_i++;
|
||||
aig_map[bit] = 2*aig_m;
|
||||
}
|
||||
|
||||
for (auto &c : co_bits) {
|
||||
RTLIL::SigBit bit = std::get<0>(c);
|
||||
std::get<4>(c) = ordered_outputs[bit] = aig_o++;
|
||||
aig_outputs.push_back(bit2aig(bit));
|
||||
}
|
||||
|
||||
for (auto bit : output_bits) {
|
||||
ordered_outputs[bit] = aig_o++;
|
||||
aig_outputs.push_back(bit2aig(bit));
|
||||
}
|
||||
|
||||
if (output_bits.empty()) {
|
||||
aig_o++;
|
||||
aig_outputs.push_back(0);
|
||||
omode = true;
|
||||
}
|
||||
}
|
||||
|
||||
void write_aiger(std::ostream &f, bool ascii_mode)
|
||||
{
|
||||
int aig_obc = aig_o;
|
||||
int aig_obcj = aig_obc;
|
||||
int aig_obcjf = aig_obcj;
|
||||
|
||||
log_assert(aig_m == aig_i + aig_l + aig_a);
|
||||
log_assert(aig_obcjf == GetSize(aig_outputs));
|
||||
|
||||
f << stringf("%s %d %d %d %d %d", ascii_mode ? "aag" : "aig", aig_m, aig_i, aig_l, aig_o, aig_a);
|
||||
f << stringf("\n");
|
||||
|
||||
if (ascii_mode)
|
||||
{
|
||||
for (int i = 0; i < aig_i; i++)
|
||||
f << stringf("%d\n", 2*i+2);
|
||||
|
||||
for (int i = 0; i < aig_obc; i++)
|
||||
f << stringf("%d\n", aig_outputs.at(i));
|
||||
|
||||
for (int i = aig_obc; i < aig_obcj; i++)
|
||||
f << stringf("1\n");
|
||||
|
||||
for (int i = aig_obc; i < aig_obcj; i++)
|
||||
f << stringf("%d\n", aig_outputs.at(i));
|
||||
|
||||
for (int i = aig_obcj; i < aig_obcjf; i++)
|
||||
f << stringf("%d\n", aig_outputs.at(i));
|
||||
|
||||
for (int i = 0; i < aig_a; i++)
|
||||
f << stringf("%d %d %d\n", 2*(aig_i+aig_l+i)+2, aig_gates.at(i).first, aig_gates.at(i).second);
|
||||
}
|
||||
else
|
||||
{
|
||||
for (int i = 0; i < aig_obc; i++)
|
||||
f << stringf("%d\n", aig_outputs.at(i));
|
||||
|
||||
for (int i = aig_obc; i < aig_obcj; i++)
|
||||
f << stringf("1\n");
|
||||
|
||||
for (int i = aig_obc; i < aig_obcj; i++)
|
||||
f << stringf("%d\n", aig_outputs.at(i));
|
||||
|
||||
for (int i = aig_obcj; i < aig_obcjf; i++)
|
||||
f << stringf("%d\n", aig_outputs.at(i));
|
||||
|
||||
for (int i = 0; i < aig_a; i++) {
|
||||
int lhs = 2*(aig_i+aig_l+i)+2;
|
||||
int rhs0 = aig_gates.at(i).first;
|
||||
int rhs1 = aig_gates.at(i).second;
|
||||
int delta0 = lhs - rhs0;
|
||||
int delta1 = rhs0 - rhs1;
|
||||
aiger_encode(f, delta0);
|
||||
aiger_encode(f, delta1);
|
||||
}
|
||||
}
|
||||
|
||||
f << "c";
|
||||
|
||||
if (!box_list.empty()) {
|
||||
auto write_buffer = [](std::stringstream &buffer, int i32) {
|
||||
int32_t i32_be = to_big_endian(i32);
|
||||
buffer.write(reinterpret_cast<const char*>(&i32_be), sizeof(i32_be));
|
||||
};
|
||||
|
||||
std::stringstream h_buffer;
|
||||
auto write_h_buffer = std::bind(write_buffer, std::ref(h_buffer), std::placeholders::_1);
|
||||
write_h_buffer(1);
|
||||
log_debug("ciNum = %zu\n", input_bits.size() + ci_bits.size());
|
||||
write_h_buffer(input_bits.size() + ci_bits.size());
|
||||
log_debug("coNum = %zu\n", output_bits.size() + co_bits.size());
|
||||
write_h_buffer(output_bits.size() + co_bits.size());
|
||||
log_debug("piNum = %zu\n", input_bits.size());
|
||||
write_h_buffer(input_bits.size());
|
||||
log_debug("poNum = %zu\n", output_bits.size());
|
||||
write_h_buffer(output_bits.size());
|
||||
log_debug("boxNum = %zu\n", box_list.size());
|
||||
write_h_buffer(box_list.size());
|
||||
|
||||
RTLIL::Module *holes_module = nullptr;
|
||||
holes_module = module->design->addModule("$__holes__");
|
||||
log_assert(holes_module);
|
||||
|
||||
int port_id = 1;
|
||||
int box_count = 0;
|
||||
for (auto cell : box_list) {
|
||||
RTLIL::Module* box_module = module->design->module(cell->type);
|
||||
int box_inputs = 0, box_outputs = 0;
|
||||
Cell *holes_cell = nullptr;
|
||||
if (box_module->get_bool_attribute("\\whitebox")) {
|
||||
holes_cell = holes_module->addCell(cell->name, cell->type);
|
||||
holes_cell->parameters = cell->parameters;
|
||||
}
|
||||
|
||||
// NB: Assume box_module->ports are sorted alphabetically
|
||||
// (as RTLIL::Module::fixup_ports() would do)
|
||||
for (const auto &port_name : box_module->ports) {
|
||||
RTLIL::Wire *w = box_module->wire(port_name);
|
||||
log_assert(w);
|
||||
RTLIL::Wire *holes_wire;
|
||||
RTLIL::SigSpec port_wire;
|
||||
if (w->port_input) {
|
||||
for (int i = 0; i < GetSize(w); i++) {
|
||||
box_inputs++;
|
||||
holes_wire = holes_module->wire(stringf("\\i%d", box_inputs));
|
||||
if (!holes_wire) {
|
||||
holes_wire = holes_module->addWire(stringf("\\i%d", box_inputs));
|
||||
holes_wire->port_input = true;
|
||||
holes_wire->port_id = port_id++;
|
||||
holes_module->ports.push_back(holes_wire->name);
|
||||
}
|
||||
if (holes_cell)
|
||||
port_wire.append(holes_wire);
|
||||
}
|
||||
if (!port_wire.empty())
|
||||
holes_cell->setPort(w->name, port_wire);
|
||||
}
|
||||
if (w->port_output) {
|
||||
box_outputs += GetSize(w);
|
||||
for (int i = 0; i < GetSize(w); i++) {
|
||||
if (GetSize(w) == 1)
|
||||
holes_wire = holes_module->addWire(stringf("%s.%s", cell->name.c_str(), w->name.c_str()));
|
||||
else
|
||||
holes_wire = holes_module->addWire(stringf("%s.%s[%d]", cell->name.c_str(), w->name.c_str(), i));
|
||||
holes_wire->port_output = true;
|
||||
holes_wire->port_id = port_id++;
|
||||
holes_module->ports.push_back(holes_wire->name);
|
||||
if (holes_cell)
|
||||
port_wire.append(holes_wire);
|
||||
else
|
||||
holes_module->connect(holes_wire, RTLIL::S0);
|
||||
}
|
||||
if (!port_wire.empty())
|
||||
holes_cell->setPort(w->name, port_wire);
|
||||
}
|
||||
}
|
||||
|
||||
write_h_buffer(box_inputs);
|
||||
write_h_buffer(box_outputs);
|
||||
write_h_buffer(box_module->attributes.at("\\abc_box_id").as_int());
|
||||
write_h_buffer(box_count++);
|
||||
}
|
||||
|
||||
f << "h";
|
||||
std::string buffer_str = h_buffer.str();
|
||||
int32_t buffer_size_be = to_big_endian(buffer_str.size());
|
||||
f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
|
||||
f.write(buffer_str.data(), buffer_str.size());
|
||||
|
||||
std::stringstream r_buffer;
|
||||
auto write_r_buffer = std::bind(write_buffer, std::ref(r_buffer), std::placeholders::_1);
|
||||
write_r_buffer(0);
|
||||
|
||||
f << "r";
|
||||
buffer_str = r_buffer.str();
|
||||
buffer_size_be = to_big_endian(buffer_str.size());
|
||||
f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
|
||||
f.write(buffer_str.data(), buffer_str.size());
|
||||
|
||||
if (holes_module) {
|
||||
log_push();
|
||||
|
||||
// NB: fixup_ports() will sort ports by name
|
||||
//holes_module->fixup_ports();
|
||||
holes_module->check();
|
||||
|
||||
holes_module->design->selection_stack.emplace_back(false);
|
||||
RTLIL::Selection& sel = holes_module->design->selection_stack.back();
|
||||
sel.select(holes_module);
|
||||
|
||||
// TODO: Should not need to opt_merge if we only instantiate
|
||||
// each box type once...
|
||||
Pass::call(holes_module->design, "opt_merge -share_all");
|
||||
|
||||
Pass::call(holes_module->design, "flatten -wb");
|
||||
|
||||
// TODO: Should techmap/aigmap/check all lib_whitebox-es just once,
|
||||
// instead of per write_xaiger call
|
||||
Pass::call(holes_module->design, "techmap");
|
||||
Pass::call(holes_module->design, "aigmap");
|
||||
for (auto cell : holes_module->cells())
|
||||
if (!cell->type.in("$_NOT_", "$_AND_"))
|
||||
log_error("Whitebox contents cannot be represented as AIG. Please verify whiteboxes are synthesisable.\n");
|
||||
|
||||
Pass::call(holes_module->design, "clean -purge");
|
||||
|
||||
std::stringstream a_buffer;
|
||||
XAigerWriter writer(holes_module, true /* holes_mode */);
|
||||
writer.write_aiger(a_buffer, false /*ascii_mode*/);
|
||||
|
||||
holes_module->design->selection_stack.pop_back();
|
||||
|
||||
f << "a";
|
||||
std::string buffer_str = a_buffer.str();
|
||||
int32_t buffer_size_be = to_big_endian(buffer_str.size());
|
||||
f.write(reinterpret_cast<const char*>(&buffer_size_be), sizeof(buffer_size_be));
|
||||
f.write(buffer_str.data(), buffer_str.size());
|
||||
holes_module->design->remove(holes_module);
|
||||
|
||||
log_pop();
|
||||
}
|
||||
}
|
||||
|
||||
f << stringf("Generated by %s\n", yosys_version_str);
|
||||
}
|
||||
|
||||
void write_map(std::ostream &f, bool verbose_map)
|
||||
{
|
||||
dict<int, string> input_lines;
|
||||
dict<int, string> output_lines;
|
||||
dict<int, string> wire_lines;
|
||||
|
||||
for (auto wire : module->wires())
|
||||
{
|
||||
//if (!verbose_map && wire->name[0] == '$')
|
||||
// continue;
|
||||
|
||||
SigSpec sig = sigmap(wire);
|
||||
|
||||
for (int i = 0; i < GetSize(wire); i++)
|
||||
{
|
||||
RTLIL::SigBit b(wire, i);
|
||||
if (input_bits.count(b)) {
|
||||
int a = aig_map.at(b);
|
||||
log_assert((a & 1) == 0);
|
||||
input_lines[a] += stringf("input %d %d %s\n", (a >> 1)-1, i, log_id(wire));
|
||||
}
|
||||
|
||||
if (output_bits.count(b)) {
|
||||
int o = ordered_outputs.at(b);
|
||||
output_lines[o] += stringf("output %lu %d %s\n", o - co_bits.size(), i, log_id(wire));
|
||||
continue;
|
||||
}
|
||||
|
||||
if (verbose_map) {
|
||||
if (aig_map.count(sig[i]) == 0)
|
||||
continue;
|
||||
|
||||
int a = aig_map.at(sig[i]);
|
||||
wire_lines[a] += stringf("wire %d %d %s\n", a, i, log_id(wire));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
input_lines.sort();
|
||||
for (auto &it : input_lines)
|
||||
f << it.second;
|
||||
log_assert(input_lines.size() == input_bits.size());
|
||||
|
||||
int box_count = 0;
|
||||
for (auto cell : box_list)
|
||||
f << stringf("box %d %d %s\n", box_count++, 0, log_id(cell->name));
|
||||
|
||||
output_lines.sort();
|
||||
for (auto &it : output_lines)
|
||||
f << it.second;
|
||||
log_assert(output_lines.size() == output_bits.size());
|
||||
if (omode && output_bits.empty())
|
||||
f << "output " << output_lines.size() << " 0 $__dummy__\n";
|
||||
|
||||
wire_lines.sort();
|
||||
for (auto &it : wire_lines)
|
||||
f << it.second;
|
||||
}
|
||||
};
|
||||
|
||||
struct XAigerBackend : public Backend {
|
||||
XAigerBackend() : Backend("xaiger", "write design to XAIGER file") { }
|
||||
void help() YS_OVERRIDE
|
||||
{
|
||||
// |---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|---v---|
|
||||
log("\n");
|
||||
log(" write_xaiger [options] [filename]\n");
|
||||
log("\n");
|
||||
log("Write the current design to an XAIGER file. The design must be flattened and\n");
|
||||
log("all unsupported cells will be converted into psuedo-inputs and pseudo-outputs.\n");
|
||||
log("\n");
|
||||
log(" -ascii\n");
|
||||
log(" write ASCII version of AIGER format\n");
|
||||
log("\n");
|
||||
log(" -map <filename>\n");
|
||||
log(" write an extra file with port and latch symbols\n");
|
||||
log("\n");
|
||||
log(" -vmap <filename>\n");
|
||||
log(" like -map, but more verbose\n");
|
||||
log("\n");
|
||||
}
|
||||
void execute(std::ostream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
||||
{
|
||||
bool ascii_mode = false;
|
||||
bool verbose_map = false;
|
||||
std::string map_filename;
|
||||
|
||||
log_header(design, "Executing XAIGER backend.\n");
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++)
|
||||
{
|
||||
if (args[argidx] == "-ascii") {
|
||||
ascii_mode = true;
|
||||
continue;
|
||||
}
|
||||
if (map_filename.empty() && args[argidx] == "-map" && argidx+1 < args.size()) {
|
||||
map_filename = args[++argidx];
|
||||
continue;
|
||||
}
|
||||
if (map_filename.empty() && args[argidx] == "-vmap" && argidx+1 < args.size()) {
|
||||
map_filename = args[++argidx];
|
||||
verbose_map = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(f, filename, args, argidx);
|
||||
|
||||
Module *top_module = design->top_module();
|
||||
|
||||
if (top_module == nullptr)
|
||||
log_error("Can't find top module in current design!\n");
|
||||
|
||||
XAigerWriter writer(top_module);
|
||||
writer.write_aiger(*f, ascii_mode);
|
||||
|
||||
if (!map_filename.empty()) {
|
||||
std::ofstream mapf;
|
||||
mapf.open(map_filename.c_str(), std::ofstream::trunc);
|
||||
if (mapf.fail())
|
||||
log_error("Can't open file `%s' for writing: %s\n", map_filename.c_str(), strerror(errno));
|
||||
writer.write_map(mapf, verbose_map);
|
||||
}
|
||||
}
|
||||
} XAigerBackend;
|
||||
|
||||
PRIVATE_NAMESPACE_END
|
||||
|
|
@ -2,7 +2,7 @@
|
|||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
|
||||
* Eddie Hung <eddie@fpgeh.com>
|
||||
* 2019 Eddie Hung <eddie@fpgeh.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
|
|
@ -22,19 +22,190 @@
|
|||
// Armin Biere. The AIGER And-Inverter Graph (AIG) Format Version 20071012. Technical Report 07/1, October 2011, FMV Reports Series, Institute for Formal Models and Verification, Johannes Kepler University, Altenbergerstr. 69, 4040 Linz, Austria.
|
||||
// http://fmv.jku.at/papers/Biere-FMV-TR-07-1.pdf
|
||||
|
||||
#ifndef _WIN32
|
||||
#include <libgen.h>
|
||||
// https://stackoverflow.com/a/46137633
|
||||
#ifdef _MSC_VER
|
||||
#include <stdlib.h>
|
||||
#define __builtin_bswap32 _byteswap_ulong
|
||||
#elif defined(__APPLE__)
|
||||
#include <libkern/OSByteOrder.h>
|
||||
#define __builtin_bswap32 OSSwapInt32
|
||||
#endif
|
||||
#include <array>
|
||||
#include <inttypes.h>
|
||||
|
||||
#include "kernel/yosys.h"
|
||||
#include "kernel/sigtools.h"
|
||||
#include "kernel/celltypes.h"
|
||||
#include "aigerparse.h"
|
||||
|
||||
YOSYS_NAMESPACE_BEGIN
|
||||
|
||||
AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name)
|
||||
: design(design), f(f), clk_name(clk_name)
|
||||
inline int32_t from_big_endian(int32_t i32) {
|
||||
#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__
|
||||
return __builtin_bswap32(i32);
|
||||
#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
|
||||
return i32;
|
||||
#else
|
||||
#error "Unknown endianness"
|
||||
#endif
|
||||
}
|
||||
|
||||
#define log_debug2(...) ;
|
||||
//#define log_debug2(...) log_debug(__VA_ARGS__)
|
||||
|
||||
struct ConstEvalAig
|
||||
{
|
||||
RTLIL::Module *module;
|
||||
dict<RTLIL::SigBit, RTLIL::State> values_map;
|
||||
dict<RTLIL::SigBit, RTLIL::Cell*> sig2driver;
|
||||
dict<SigBit, pool<RTLIL::SigBit>> sig2deps;
|
||||
|
||||
ConstEvalAig(RTLIL::Module *module) : module(module)
|
||||
{
|
||||
for (auto &it : module->cells_) {
|
||||
if (!yosys_celltypes.cell_known(it.second->type))
|
||||
continue;
|
||||
for (auto &it2 : it.second->connections())
|
||||
if (yosys_celltypes.cell_output(it.second->type, it2.first)) {
|
||||
auto r = sig2driver.insert(std::make_pair(it2.second, it.second));
|
||||
log_assert(r.second);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void clear()
|
||||
{
|
||||
values_map.clear();
|
||||
sig2deps.clear();
|
||||
}
|
||||
|
||||
void set(RTLIL::SigBit sig, RTLIL::State value)
|
||||
{
|
||||
auto it = values_map.find(sig);
|
||||
#ifndef NDEBUG
|
||||
if (it != values_map.end()) {
|
||||
RTLIL::State current_val = it->second;
|
||||
log_assert(current_val == value);
|
||||
}
|
||||
#endif
|
||||
if (it != values_map.end())
|
||||
it->second = value;
|
||||
else
|
||||
values_map[sig] = value;
|
||||
}
|
||||
|
||||
void set_incremental(RTLIL::SigSpec sig, RTLIL::Const value)
|
||||
{
|
||||
log_assert(GetSize(sig) == GetSize(value));
|
||||
|
||||
for (int i = 0; i < GetSize(sig); i++) {
|
||||
auto it = values_map.find(sig[i]);
|
||||
if (it != values_map.end()) {
|
||||
RTLIL::State current_val = it->second;
|
||||
if (current_val != value[i])
|
||||
for (auto dep : sig2deps[sig[i]])
|
||||
values_map.erase(dep);
|
||||
it->second = value[i];
|
||||
}
|
||||
else
|
||||
values_map[sig[i]] = value[i];
|
||||
}
|
||||
}
|
||||
|
||||
void compute_deps(RTLIL::SigBit output, const pool<RTLIL::SigBit> &inputs)
|
||||
{
|
||||
sig2deps[output].insert(output);
|
||||
|
||||
RTLIL::Cell *cell = sig2driver.at(output);
|
||||
RTLIL::SigBit sig_a = cell->getPort("\\A");
|
||||
sig2deps[sig_a].reserve(sig2deps[sig_a].size() + sig2deps[output].size()); // Reserve so that any invalidation
|
||||
// that may occur does so here, and
|
||||
// not mid insertion (below)
|
||||
sig2deps[sig_a].insert(sig2deps[output].begin(), sig2deps[output].end());
|
||||
if (!inputs.count(sig_a))
|
||||
compute_deps(sig_a, inputs);
|
||||
|
||||
if (cell->type == "$_AND_") {
|
||||
RTLIL::SigSpec sig_b = cell->getPort("\\B");
|
||||
sig2deps[sig_b].reserve(sig2deps[sig_b].size() + sig2deps[output].size()); // Reserve so that any invalidation
|
||||
// that may occur does so here, and
|
||||
// not mid insertion (below)
|
||||
sig2deps[sig_b].insert(sig2deps[output].begin(), sig2deps[output].end());
|
||||
|
||||
if (!inputs.count(sig_b))
|
||||
compute_deps(sig_b, inputs);
|
||||
}
|
||||
else if (cell->type == "$_NOT_") {
|
||||
}
|
||||
else log_abort();
|
||||
}
|
||||
|
||||
bool eval(RTLIL::Cell *cell)
|
||||
{
|
||||
RTLIL::SigBit sig_y = cell->getPort("\\Y");
|
||||
if (values_map.count(sig_y))
|
||||
return true;
|
||||
|
||||
RTLIL::SigBit sig_a = cell->getPort("\\A");
|
||||
if (!eval(sig_a))
|
||||
return false;
|
||||
|
||||
RTLIL::State eval_ret = RTLIL::Sx;
|
||||
if (cell->type == "$_NOT_") {
|
||||
if (sig_a == RTLIL::S0) eval_ret = RTLIL::S1;
|
||||
else if (sig_a == RTLIL::S1) eval_ret = RTLIL::S0;
|
||||
}
|
||||
else if (cell->type == "$_AND_") {
|
||||
if (sig_a == RTLIL::S0) {
|
||||
eval_ret = RTLIL::S0;
|
||||
goto eval_end;
|
||||
}
|
||||
|
||||
{
|
||||
RTLIL::SigBit sig_b = cell->getPort("\\B");
|
||||
if (!eval(sig_b))
|
||||
return false;
|
||||
if (sig_b == RTLIL::S0) {
|
||||
eval_ret = RTLIL::S0;
|
||||
goto eval_end;
|
||||
}
|
||||
|
||||
if (sig_a != RTLIL::S1 || sig_b != RTLIL::S1)
|
||||
goto eval_end;
|
||||
|
||||
eval_ret = RTLIL::S1;
|
||||
}
|
||||
}
|
||||
else log_abort();
|
||||
|
||||
eval_end:
|
||||
set(sig_y, eval_ret);
|
||||
return true;
|
||||
}
|
||||
|
||||
bool eval(RTLIL::SigBit &sig)
|
||||
{
|
||||
auto it = values_map.find(sig);
|
||||
if (it != values_map.end()) {
|
||||
sig = it->second;
|
||||
return true;
|
||||
}
|
||||
|
||||
RTLIL::Cell *cell = sig2driver.at(sig);
|
||||
if (!eval(cell))
|
||||
return false;
|
||||
|
||||
it = values_map.find(sig);
|
||||
if (it != values_map.end()) {
|
||||
sig = it->second;
|
||||
return true;
|
||||
}
|
||||
|
||||
return false;
|
||||
}
|
||||
};
|
||||
|
||||
AigerReader::AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports)
|
||||
: design(design), f(f), clk_name(clk_name), map_filename(map_filename), wideports(wideports)
|
||||
{
|
||||
module = new RTLIL::Module;
|
||||
module->name = module_name;
|
||||
|
|
@ -73,6 +244,8 @@ end_of_header:
|
|||
log_debug("M=%u I=%u L=%u O=%u A=%u B=%u C=%u J=%u F=%u\n", M, I, L, O, A, B, C, J, F);
|
||||
|
||||
line_count = 1;
|
||||
piNum = 0;
|
||||
flopNum = 0;
|
||||
|
||||
if (header == "aag")
|
||||
parse_aiger_ascii();
|
||||
|
|
@ -81,21 +254,10 @@ end_of_header:
|
|||
else
|
||||
log_abort();
|
||||
|
||||
RTLIL::Wire* n0 = module->wire("\\n0");
|
||||
RTLIL::Wire* n0 = module->wire("\\__0__");
|
||||
if (n0)
|
||||
module->connect(n0, RTLIL::S0);
|
||||
|
||||
for (unsigned i = 0; i < outputs.size(); ++i) {
|
||||
RTLIL::Wire *wire = outputs[i];
|
||||
if (wire->port_input) {
|
||||
RTLIL::Wire *o_wire = module->addWire(wire->name.str() + "_o");
|
||||
o_wire->port_output = true;
|
||||
wire->port_output = false;
|
||||
module->connect(o_wire, wire);
|
||||
outputs[i] = o_wire;
|
||||
}
|
||||
}
|
||||
|
||||
// Parse footer (symbol table, comments, etc.)
|
||||
unsigned l1;
|
||||
std::string s;
|
||||
|
|
@ -131,36 +293,195 @@ end_of_header:
|
|||
std::getline(f, line); // Ignore up to start of next line
|
||||
}
|
||||
|
||||
module->fixup_ports();
|
||||
design->add(module);
|
||||
post_process();
|
||||
}
|
||||
|
||||
static uint32_t parse_xaiger_literal(std::istream &f)
|
||||
{
|
||||
uint32_t l;
|
||||
f.read(reinterpret_cast<char*>(&l), sizeof(l));
|
||||
if (f.gcount() != sizeof(l))
|
||||
log_error("Offset %" PRId64 ": unable to read literal!\n", static_cast<int64_t>(f.tellg()));
|
||||
return from_big_endian(l);
|
||||
}
|
||||
|
||||
static RTLIL::Wire* createWireIfNotExists(RTLIL::Module *module, unsigned literal)
|
||||
{
|
||||
const unsigned variable = literal >> 1;
|
||||
const bool invert = literal & 1;
|
||||
RTLIL::IdString wire_name(stringf("\\n%d%s", variable, invert ? "_inv" : "")); // FIXME: is "_inv" the right suffix?
|
||||
RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : ""));
|
||||
RTLIL::Wire *wire = module->wire(wire_name);
|
||||
if (wire) return wire;
|
||||
log_debug("Creating %s\n", wire_name.c_str());
|
||||
log_debug2("Creating %s\n", wire_name.c_str());
|
||||
wire = module->addWire(wire_name);
|
||||
wire->port_input = wire->port_output = false;
|
||||
if (!invert) return wire;
|
||||
RTLIL::IdString wire_inv_name(stringf("\\n%d", variable));
|
||||
RTLIL::IdString wire_inv_name(stringf("\\__%d__", variable));
|
||||
RTLIL::Wire *wire_inv = module->wire(wire_inv_name);
|
||||
if (wire_inv) {
|
||||
if (module->cell(wire_inv_name)) return wire;
|
||||
}
|
||||
else {
|
||||
log_debug("Creating %s\n", wire_inv_name.c_str());
|
||||
log_debug2("Creating %s\n", wire_inv_name.c_str());
|
||||
wire_inv = module->addWire(wire_inv_name);
|
||||
wire_inv->port_input = wire_inv->port_output = false;
|
||||
}
|
||||
|
||||
log_debug("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
|
||||
module->addNotGate(stringf("\\n%d_not", variable), wire_inv, wire); // FIXME: is "_not" the right suffix?
|
||||
log_debug2("Creating %s = ~%s\n", wire_name.c_str(), wire_inv_name.c_str());
|
||||
module->addNotGate(stringf("\\__%d__$not", variable), wire_inv, wire);
|
||||
|
||||
return wire;
|
||||
}
|
||||
|
||||
void AigerReader::parse_xaiger()
|
||||
{
|
||||
std::string header;
|
||||
f >> header;
|
||||
if (header != "aag" && header != "aig")
|
||||
log_error("Unsupported AIGER file!\n");
|
||||
|
||||
// Parse rest of header
|
||||
if (!(f >> M >> I >> L >> O >> A))
|
||||
log_error("Invalid AIGER header\n");
|
||||
|
||||
// Optional values
|
||||
B = C = J = F = 0;
|
||||
|
||||
std::string line;
|
||||
std::getline(f, line); // Ignore up to start of next line, as standard
|
||||
// says anything that follows could be used for
|
||||
// optional sections
|
||||
|
||||
log_debug("M=%u I=%u L=%u O=%u A=%u\n", M, I, L, O, A);
|
||||
|
||||
line_count = 1;
|
||||
piNum = 0;
|
||||
flopNum = 0;
|
||||
|
||||
if (header == "aag")
|
||||
parse_aiger_ascii();
|
||||
else if (header == "aig")
|
||||
parse_aiger_binary();
|
||||
else
|
||||
log_abort();
|
||||
|
||||
RTLIL::Wire* n0 = module->wire("\\__0__");
|
||||
if (n0)
|
||||
module->connect(n0, RTLIL::S0);
|
||||
|
||||
dict<int,IdString> box_lookup;
|
||||
for (auto m : design->modules()) {
|
||||
auto it = m->attributes.find("\\abc_box_id");
|
||||
if (it == m->attributes.end())
|
||||
continue;
|
||||
if (m->name.begins_with("$paramod"))
|
||||
continue;
|
||||
auto r = box_lookup.insert(std::make_pair(it->second.as_int(), m->name));
|
||||
log_assert(r.second);
|
||||
}
|
||||
|
||||
// Parse footer (symbol table, comments, etc.)
|
||||
std::string s;
|
||||
bool comment_seen = false;
|
||||
for (int c = f.peek(); c != EOF; c = f.peek()) {
|
||||
if (comment_seen || c == 'c') {
|
||||
if (!comment_seen) {
|
||||
f.ignore(1);
|
||||
c = f.peek();
|
||||
comment_seen = true;
|
||||
}
|
||||
if (c == '\n')
|
||||
break;
|
||||
f.ignore(1);
|
||||
// XAIGER extensions
|
||||
if (c == 'm') {
|
||||
uint32_t dataSize = parse_xaiger_literal(f);
|
||||
uint32_t lutNum = parse_xaiger_literal(f);
|
||||
uint32_t lutSize = parse_xaiger_literal(f);
|
||||
log_debug("m: dataSize=%u lutNum=%u lutSize=%u\n", dataSize, lutNum, lutSize);
|
||||
ConstEvalAig ce(module);
|
||||
for (unsigned i = 0; i < lutNum; ++i) {
|
||||
uint32_t rootNodeID = parse_xaiger_literal(f);
|
||||
uint32_t cutLeavesM = parse_xaiger_literal(f);
|
||||
log_debug2("rootNodeID=%d cutLeavesM=%d\n", rootNodeID, cutLeavesM);
|
||||
RTLIL::Wire *output_sig = module->wire(stringf("\\__%d__", rootNodeID));
|
||||
uint32_t nodeID;
|
||||
RTLIL::SigSpec input_sig;
|
||||
for (unsigned j = 0; j < cutLeavesM; ++j) {
|
||||
nodeID = parse_xaiger_literal(f);
|
||||
log_debug2("\t%u\n", nodeID);
|
||||
RTLIL::Wire *wire = module->wire(stringf("\\__%d__", nodeID));
|
||||
log_assert(wire);
|
||||
input_sig.append(wire);
|
||||
}
|
||||
// TODO: Compute LUT mask from AIG in less than O(2 ** input_sig.size())
|
||||
ce.clear();
|
||||
ce.compute_deps(output_sig, input_sig.to_sigbit_pool());
|
||||
RTLIL::Const lut_mask(RTLIL::State::Sx, 1 << input_sig.size());
|
||||
for (int j = 0; j < (1 << cutLeavesM); ++j) {
|
||||
int gray = j ^ (j >> 1);
|
||||
ce.set_incremental(input_sig, RTLIL::Const{gray, static_cast<int>(cutLeavesM)});
|
||||
RTLIL::SigBit o(output_sig);
|
||||
bool success = ce.eval(o);
|
||||
log_assert(success);
|
||||
log_assert(o.wire == nullptr);
|
||||
lut_mask[gray] = o.data;
|
||||
}
|
||||
RTLIL::Cell *output_cell = module->cell(stringf("\\__%d__$and", rootNodeID));
|
||||
log_assert(output_cell);
|
||||
module->remove(output_cell);
|
||||
module->addLut(stringf("\\__%d__$lut", rootNodeID), input_sig, output_sig, std::move(lut_mask));
|
||||
}
|
||||
}
|
||||
else if (c == 'r') {
|
||||
uint32_t dataSize = parse_xaiger_literal(f);
|
||||
flopNum = parse_xaiger_literal(f);
|
||||
log_assert(dataSize == (flopNum+1) * sizeof(uint32_t));
|
||||
f.ignore(flopNum * sizeof(uint32_t));
|
||||
}
|
||||
else if (c == 'n') {
|
||||
parse_xaiger_literal(f);
|
||||
f >> s;
|
||||
log_debug("n: '%s'\n", s.c_str());
|
||||
}
|
||||
else if (c == 'h') {
|
||||
f.ignore(sizeof(uint32_t));
|
||||
uint32_t version = parse_xaiger_literal(f);
|
||||
log_assert(version == 1);
|
||||
uint32_t ciNum = parse_xaiger_literal(f);
|
||||
log_debug("ciNum = %u\n", ciNum);
|
||||
uint32_t coNum = parse_xaiger_literal(f);
|
||||
log_debug("coNum = %u\n", coNum);
|
||||
piNum = parse_xaiger_literal(f);
|
||||
log_debug("piNum = %u\n", piNum);
|
||||
uint32_t poNum = parse_xaiger_literal(f);
|
||||
log_debug("poNum = %u\n", poNum);
|
||||
uint32_t boxNum = parse_xaiger_literal(f);
|
||||
log_debug("boxNum = %u\n", poNum);
|
||||
for (unsigned i = 0; i < boxNum; i++) {
|
||||
f.ignore(2*sizeof(uint32_t));
|
||||
uint32_t boxUniqueId = parse_xaiger_literal(f);
|
||||
log_assert(boxUniqueId > 0);
|
||||
uint32_t oldBoxNum = parse_xaiger_literal(f);
|
||||
RTLIL::Cell* cell = module->addCell(stringf("$__box%u__", oldBoxNum), box_lookup.at(boxUniqueId));
|
||||
boxes.emplace_back(cell);
|
||||
}
|
||||
}
|
||||
else if (c == 'a' || c == 'i' || c == 'o') {
|
||||
uint32_t dataSize = parse_xaiger_literal(f);
|
||||
f.ignore(dataSize);
|
||||
}
|
||||
else {
|
||||
break;
|
||||
}
|
||||
}
|
||||
else
|
||||
log_error("Line %u: cannot interpret first character '%c'!\n", line_count, c);
|
||||
}
|
||||
|
||||
post_process();
|
||||
}
|
||||
|
||||
void AigerReader::parse_aiger_ascii()
|
||||
{
|
||||
std::string line;
|
||||
|
|
@ -172,8 +493,8 @@ void AigerReader::parse_aiger_ascii()
|
|||
for (unsigned i = 1; i <= I; ++i, ++line_count) {
|
||||
if (!(f >> l1))
|
||||
log_error("Line %u cannot be interpreted as an input!\n", line_count);
|
||||
log_debug("%d is an input\n", l1);
|
||||
log_assert(!(l1 & 1)); // TODO: Inputs can't be inverted?
|
||||
log_debug2("%d is an input\n", l1);
|
||||
log_assert(!(l1 & 1)); // Inputs can't be inverted
|
||||
RTLIL::Wire *wire = createWireIfNotExists(module, l1);
|
||||
wire->port_input = true;
|
||||
inputs.push_back(wire);
|
||||
|
|
@ -182,17 +503,19 @@ void AigerReader::parse_aiger_ascii()
|
|||
// Parse latches
|
||||
RTLIL::Wire *clk_wire = nullptr;
|
||||
if (L > 0) {
|
||||
log_assert(clk_name != "");
|
||||
clk_wire = module->wire(clk_name);
|
||||
log_assert(!clk_wire);
|
||||
log_debug("Creating %s\n", clk_name.c_str());
|
||||
log_debug2("Creating %s\n", clk_name.c_str());
|
||||
clk_wire = module->addWire(clk_name);
|
||||
clk_wire->port_input = true;
|
||||
clk_wire->port_output = false;
|
||||
}
|
||||
for (unsigned i = 0; i < L; ++i, ++line_count) {
|
||||
if (!(f >> l1 >> l2))
|
||||
log_error("Line %u cannot be interpreted as a latch!\n", line_count);
|
||||
log_debug("%d %d is a latch\n", l1, l2);
|
||||
log_assert(!(l1 & 1)); // TODO: Latch outputs can't be inverted?
|
||||
log_debug2("%d %d is a latch\n", l1, l2);
|
||||
log_assert(!(l1 & 1));
|
||||
RTLIL::Wire *q_wire = createWireIfNotExists(module, l1);
|
||||
RTLIL::Wire *d_wire = createWireIfNotExists(module, l2);
|
||||
|
||||
|
|
@ -208,7 +531,7 @@ void AigerReader::parse_aiger_ascii()
|
|||
else if (l3 == 1)
|
||||
q_wire->attributes["\\init"] = RTLIL::S1;
|
||||
else if (l3 == l1) {
|
||||
//q_wire->attributes["\\init"] = RTLIL::Const(RTLIL::State::Sx);
|
||||
//q_wire->attributes["\\init"] = RTLIL::Sx;
|
||||
}
|
||||
else
|
||||
log_error("Line %u has invalid reset literal for latch!\n", line_count);
|
||||
|
|
@ -225,8 +548,18 @@ void AigerReader::parse_aiger_ascii()
|
|||
if (!(f >> l1))
|
||||
log_error("Line %u cannot be interpreted as an output!\n", line_count);
|
||||
|
||||
log_debug("%d is an output\n", l1);
|
||||
RTLIL::Wire *wire = createWireIfNotExists(module, l1);
|
||||
log_debug2("%d is an output\n", l1);
|
||||
const unsigned variable = l1 >> 1;
|
||||
const bool invert = l1 & 1;
|
||||
RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "b" the right suffix?
|
||||
RTLIL::Wire *wire = module->wire(wire_name);
|
||||
if (!wire)
|
||||
wire = createWireIfNotExists(module, l1);
|
||||
else if (wire->port_input || wire->port_output) {
|
||||
RTLIL::Wire *new_wire = module->addWire(NEW_ID);
|
||||
module->connect(new_wire, wire);
|
||||
wire = new_wire;
|
||||
}
|
||||
wire->port_output = true;
|
||||
outputs.push_back(wire);
|
||||
}
|
||||
|
|
@ -236,7 +569,7 @@ void AigerReader::parse_aiger_ascii()
|
|||
if (!(f >> l1))
|
||||
log_error("Line %u cannot be interpreted as a bad state property!\n", line_count);
|
||||
|
||||
log_debug("%d is a bad state property\n", l1);
|
||||
log_debug2("%d is a bad state property\n", l1);
|
||||
RTLIL::Wire *wire = createWireIfNotExists(module, l1);
|
||||
wire->port_output = true;
|
||||
bad_properties.push_back(wire);
|
||||
|
|
@ -259,12 +592,12 @@ void AigerReader::parse_aiger_ascii()
|
|||
if (!(f >> l1 >> l2 >> l3))
|
||||
log_error("Line %u cannot be interpreted as an AND!\n", line_count);
|
||||
|
||||
log_debug("%d %d %d is an AND\n", l1, l2, l3);
|
||||
log_assert(!(l1 & 1)); // TODO: Output of ANDs can't be inverted?
|
||||
log_debug2("%d %d %d is an AND\n", l1, l2, l3);
|
||||
log_assert(!(l1 & 1));
|
||||
RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
|
||||
RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
|
||||
RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
|
||||
module->addAndGate(NEW_ID, i1_wire, i2_wire, o_wire);
|
||||
module->addAndGate(o_wire->name.str() + "$and", i1_wire, i2_wire, o_wire);
|
||||
}
|
||||
std::getline(f, line); // Ignore up to start of next line
|
||||
}
|
||||
|
|
@ -285,19 +618,23 @@ void AigerReader::parse_aiger_binary()
|
|||
|
||||
// Parse inputs
|
||||
for (unsigned i = 1; i <= I; ++i) {
|
||||
log_debug2("%d is an input\n", i);
|
||||
RTLIL::Wire *wire = createWireIfNotExists(module, i << 1);
|
||||
wire->port_input = true;
|
||||
log_assert(!wire->port_output);
|
||||
inputs.push_back(wire);
|
||||
}
|
||||
|
||||
// Parse latches
|
||||
RTLIL::Wire *clk_wire = nullptr;
|
||||
if (L > 0) {
|
||||
log_assert(clk_name != "");
|
||||
clk_wire = module->wire(clk_name);
|
||||
log_assert(!clk_wire);
|
||||
log_debug("Creating %s\n", clk_name.c_str());
|
||||
log_debug2("Creating %s\n", clk_name.c_str());
|
||||
clk_wire = module->addWire(clk_name);
|
||||
clk_wire->port_input = true;
|
||||
clk_wire->port_output = false;
|
||||
}
|
||||
l1 = (I+1) * 2;
|
||||
for (unsigned i = 0; i < L; ++i, ++line_count, l1 += 2) {
|
||||
|
|
@ -319,7 +656,7 @@ void AigerReader::parse_aiger_binary()
|
|||
else if (l3 == 1)
|
||||
q_wire->attributes["\\init"] = RTLIL::S1;
|
||||
else if (l3 == l1) {
|
||||
//q_wire->attributes["\\init"] = RTLIL::Const(RTLIL::State::Sx);
|
||||
//q_wire->attributes["\\init"] = RTLIL::Sx;
|
||||
}
|
||||
else
|
||||
log_error("Line %u has invalid reset literal for latch!\n", line_count);
|
||||
|
|
@ -336,8 +673,18 @@ void AigerReader::parse_aiger_binary()
|
|||
if (!(f >> l1))
|
||||
log_error("Line %u cannot be interpreted as an output!\n", line_count);
|
||||
|
||||
log_debug("%d is an output\n", l1);
|
||||
RTLIL::Wire *wire = createWireIfNotExists(module, l1);
|
||||
log_debug2("%d is an output\n", l1);
|
||||
const unsigned variable = l1 >> 1;
|
||||
const bool invert = l1 & 1;
|
||||
RTLIL::IdString wire_name(stringf("\\__%d%s__", variable, invert ? "b" : "")); // FIXME: is "_b" the right suffix?
|
||||
RTLIL::Wire *wire = module->wire(wire_name);
|
||||
if (!wire)
|
||||
wire = createWireIfNotExists(module, l1);
|
||||
else if (wire->port_input || wire->port_output) {
|
||||
RTLIL::Wire *new_wire = module->addWire(NEW_ID);
|
||||
module->connect(new_wire, wire);
|
||||
wire = new_wire;
|
||||
}
|
||||
wire->port_output = true;
|
||||
outputs.push_back(wire);
|
||||
}
|
||||
|
|
@ -348,7 +695,7 @@ void AigerReader::parse_aiger_binary()
|
|||
if (!(f >> l1))
|
||||
log_error("Line %u cannot be interpreted as a bad state property!\n", line_count);
|
||||
|
||||
log_debug("%d is a bad state property\n", l1);
|
||||
log_debug2("%d is a bad state property\n", l1);
|
||||
RTLIL::Wire *wire = createWireIfNotExists(module, l1);
|
||||
wire->port_output = true;
|
||||
bad_properties.push_back(wire);
|
||||
|
|
@ -374,16 +721,280 @@ void AigerReader::parse_aiger_binary()
|
|||
l2 = parse_next_delta_literal(f, l1);
|
||||
l3 = parse_next_delta_literal(f, l2);
|
||||
|
||||
log_debug("%d %d %d is an AND\n", l1, l2, l3);
|
||||
log_assert(!(l1 & 1)); // TODO: Output of ANDs can't be inverted?
|
||||
log_debug2("%d %d %d is an AND\n", l1, l2, l3);
|
||||
log_assert(!(l1 & 1));
|
||||
RTLIL::Wire *o_wire = createWireIfNotExists(module, l1);
|
||||
RTLIL::Wire *i1_wire = createWireIfNotExists(module, l2);
|
||||
RTLIL::Wire *i2_wire = createWireIfNotExists(module, l3);
|
||||
module->addAndGate(o_wire->name.str() + "$and", i1_wire, i2_wire, o_wire);
|
||||
}
|
||||
}
|
||||
|
||||
RTLIL::Cell *and_cell = module->addCell(NEW_ID, "$_AND_");
|
||||
and_cell->setPort("\\A", i1_wire);
|
||||
and_cell->setPort("\\B", i2_wire);
|
||||
and_cell->setPort("\\Y", o_wire);
|
||||
void AigerReader::post_process()
|
||||
{
|
||||
pool<IdString> seen_boxes;
|
||||
unsigned ci_count = 0, co_count = 0;
|
||||
for (auto cell : boxes) {
|
||||
RTLIL::Module* box_module = design->module(cell->type);
|
||||
log_assert(box_module);
|
||||
|
||||
if (seen_boxes.insert(cell->type).second) {
|
||||
auto it = box_module->attributes.find("\\abc_carry");
|
||||
if (it != box_module->attributes.end()) {
|
||||
RTLIL::Wire *carry_in = nullptr, *carry_out = nullptr;
|
||||
auto carry_in_out = it->second.decode_string();
|
||||
auto pos = carry_in_out.find(',');
|
||||
if (pos == std::string::npos)
|
||||
log_error("'abc_carry' attribute on module '%s' does not contain ','.\n", log_id(cell->type));
|
||||
auto carry_in_name = RTLIL::escape_id(carry_in_out.substr(0, pos));
|
||||
carry_in = box_module->wire(carry_in_name);
|
||||
if (!carry_in || !carry_in->port_input)
|
||||
log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an input port.\n", log_id(cell->type), carry_in_name.c_str());
|
||||
|
||||
auto carry_out_name = RTLIL::escape_id(carry_in_out.substr(pos+1));
|
||||
carry_out = box_module->wire(carry_out_name);
|
||||
if (!carry_out || !carry_out->port_output)
|
||||
log_error("'abc_carry' on module '%s' contains '%s' which does not exist or is not an output port.\n", log_id(cell->type), carry_out_name.c_str());
|
||||
|
||||
auto &ports = box_module->ports;
|
||||
for (auto jt = ports.begin(); jt != ports.end(); ) {
|
||||
RTLIL::Wire* w = box_module->wire(*jt);
|
||||
log_assert(w);
|
||||
if (w == carry_in || w == carry_out) {
|
||||
jt = ports.erase(jt);
|
||||
continue;
|
||||
}
|
||||
if (w->port_id > carry_in->port_id)
|
||||
--w->port_id;
|
||||
if (w->port_id > carry_out->port_id)
|
||||
--w->port_id;
|
||||
log_assert(w->port_input || w->port_output);
|
||||
log_assert(ports[w->port_id-1] == w->name);
|
||||
++jt;
|
||||
}
|
||||
ports.push_back(carry_in->name);
|
||||
carry_in->port_id = ports.size();
|
||||
ports.push_back(carry_out->name);
|
||||
carry_out->port_id = ports.size();
|
||||
}
|
||||
}
|
||||
|
||||
// NB: Assume box_module->ports are sorted alphabetically
|
||||
// (as RTLIL::Module::fixup_ports() would do)
|
||||
for (auto port_name : box_module->ports) {
|
||||
RTLIL::Wire* w = box_module->wire(port_name);
|
||||
log_assert(w);
|
||||
RTLIL::SigSpec rhs;
|
||||
RTLIL::Wire* wire = nullptr;
|
||||
for (int i = 0; i < GetSize(w); i++) {
|
||||
if (w->port_input) {
|
||||
log_assert(co_count < outputs.size());
|
||||
wire = outputs[co_count++];
|
||||
log_assert(wire);
|
||||
log_assert(wire->port_output);
|
||||
wire->port_output = false;
|
||||
}
|
||||
if (w->port_output) {
|
||||
log_assert((piNum + ci_count) < inputs.size());
|
||||
wire = inputs[piNum + ci_count++];
|
||||
log_assert(wire);
|
||||
log_assert(wire->port_input);
|
||||
wire->port_input = false;
|
||||
}
|
||||
rhs.append(wire);
|
||||
}
|
||||
cell->setPort(port_name, rhs);
|
||||
}
|
||||
}
|
||||
|
||||
dict<RTLIL::IdString, int> wideports_cache;
|
||||
|
||||
if (!map_filename.empty()) {
|
||||
std::ifstream mf(map_filename);
|
||||
std::string type, symbol;
|
||||
int variable, index;
|
||||
while (mf >> type >> variable >> index >> symbol) {
|
||||
RTLIL::IdString escaped_s = RTLIL::escape_id(symbol);
|
||||
if (type == "input") {
|
||||
log_assert(static_cast<unsigned>(variable) < inputs.size());
|
||||
RTLIL::Wire* wire = inputs[variable];
|
||||
log_assert(wire);
|
||||
log_assert(wire->port_input);
|
||||
|
||||
if (index == 0) {
|
||||
// Cope with the fact that a CI might be identical
|
||||
// to a PI (necessary due to ABC); in those cases
|
||||
// simply connect the latter to the former
|
||||
RTLIL::Wire* existing = module->wire(escaped_s);
|
||||
if (!existing)
|
||||
module->rename(wire, escaped_s);
|
||||
else {
|
||||
wire->port_input = false;
|
||||
module->connect(wire, existing);
|
||||
}
|
||||
}
|
||||
else if (index > 0) {
|
||||
std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index);
|
||||
RTLIL::Wire* existing = module->wire(indexed_name);
|
||||
if (!existing) {
|
||||
module->rename(wire, indexed_name);
|
||||
if (wideports)
|
||||
wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index);
|
||||
}
|
||||
else {
|
||||
module->connect(wire, existing);
|
||||
wire->port_input = false;
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (type == "output") {
|
||||
log_assert(static_cast<unsigned>(variable + co_count) < outputs.size());
|
||||
RTLIL::Wire* wire = outputs[variable + co_count];
|
||||
log_assert(wire);
|
||||
log_assert(wire->port_output);
|
||||
if (escaped_s == "$__dummy__") {
|
||||
wire->port_output = false;
|
||||
continue;
|
||||
}
|
||||
|
||||
if (index == 0) {
|
||||
// Cope with the fact that a CO might be identical
|
||||
// to a PO (necessary due to ABC); in those cases
|
||||
// simply connect the latter to the former
|
||||
RTLIL::Wire* existing = module->wire(escaped_s);
|
||||
if (!existing) {
|
||||
if (escaped_s.ends_with("$inout.out")) {
|
||||
wire->port_output = false;
|
||||
RTLIL::Wire *in_wire = module->wire(escaped_s.substr(0, escaped_s.size()-10));
|
||||
log_assert(in_wire);
|
||||
log_assert(in_wire->port_input && !in_wire->port_output);
|
||||
in_wire->port_output = true;
|
||||
module->connect(in_wire, wire);
|
||||
}
|
||||
else
|
||||
module->rename(wire, escaped_s);
|
||||
}
|
||||
else {
|
||||
wire->port_output = false;
|
||||
module->connect(wire, existing);
|
||||
}
|
||||
}
|
||||
else if (index > 0) {
|
||||
std::string indexed_name = stringf("%s[%d]", escaped_s.c_str(), index);
|
||||
RTLIL::Wire* existing = module->wire(indexed_name);
|
||||
if (!existing) {
|
||||
if (escaped_s.ends_with("$inout.out")) {
|
||||
wire->port_output = false;
|
||||
RTLIL::Wire *in_wire = module->wire(stringf("%s[%d]", escaped_s.substr(0, escaped_s.size()-10).c_str(), index));
|
||||
log_assert(in_wire);
|
||||
log_assert(in_wire->port_input && !in_wire->port_output);
|
||||
in_wire->port_output = true;
|
||||
module->connect(in_wire, wire);
|
||||
}
|
||||
else {
|
||||
module->rename(wire, indexed_name);
|
||||
if (wideports)
|
||||
wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index);
|
||||
}
|
||||
}
|
||||
else {
|
||||
module->connect(wire, existing);
|
||||
wire->port_output = false;
|
||||
}
|
||||
}
|
||||
}
|
||||
else if (type == "box") {
|
||||
RTLIL::Cell* cell = module->cell(stringf("$__box%d__", variable));
|
||||
if (cell) { // ABC could have optimised this box away
|
||||
module->rename(cell, escaped_s);
|
||||
RTLIL::Module* box_module = design->module(cell->type);
|
||||
log_assert(box_module);
|
||||
|
||||
for (const auto &i : cell->connections()) {
|
||||
RTLIL::IdString port_name = i.first;
|
||||
RTLIL::SigSpec rhs = i.second;
|
||||
int index = 0;
|
||||
for (auto bit : rhs.bits()) {
|
||||
RTLIL::Wire* wire = bit.wire;
|
||||
RTLIL::IdString escaped_s = RTLIL::escape_id(stringf("%s.%s", log_id(cell), log_id(port_name)));
|
||||
if (index == 0)
|
||||
module->rename(wire, escaped_s);
|
||||
else if (index > 0) {
|
||||
module->rename(wire, stringf("%s[%d]", escaped_s.c_str(), index));
|
||||
if (wideports)
|
||||
wideports_cache[escaped_s] = std::max(wideports_cache[escaped_s], index);
|
||||
}
|
||||
index++;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
else
|
||||
log_error("Symbol type '%s' not recognised.\n", type.c_str());
|
||||
}
|
||||
}
|
||||
|
||||
for (auto &wp : wideports_cache) {
|
||||
auto name = wp.first;
|
||||
int width = wp.second + 1;
|
||||
|
||||
RTLIL::Wire *wire = module->wire(name);
|
||||
if (wire)
|
||||
module->rename(wire, RTLIL::escape_id(stringf("%s[%d]", name.c_str(), 0)));
|
||||
|
||||
// Do not make ports with a mix of input/output into
|
||||
// wide ports
|
||||
bool port_input = false, port_output = false;
|
||||
for (int i = 0; i < width; i++) {
|
||||
RTLIL::IdString other_name = name.str() + stringf("[%d]", i);
|
||||
RTLIL::Wire *other_wire = module->wire(other_name);
|
||||
if (other_wire) {
|
||||
port_input = port_input || other_wire->port_input;
|
||||
port_output = port_output || other_wire->port_output;
|
||||
}
|
||||
}
|
||||
|
||||
wire = module->addWire(name, width);
|
||||
wire->port_input = port_input;
|
||||
wire->port_output = port_output;
|
||||
|
||||
for (int i = 0; i < width; i++) {
|
||||
RTLIL::IdString other_name = name.str() + stringf("[%d]", i);
|
||||
RTLIL::Wire *other_wire = module->wire(other_name);
|
||||
if (other_wire) {
|
||||
other_wire->port_input = false;
|
||||
other_wire->port_output = false;
|
||||
}
|
||||
if (wire->port_input) {
|
||||
if (other_wire)
|
||||
module->connect(other_wire, SigSpec(wire, i));
|
||||
}
|
||||
else {
|
||||
// Since we skip POs that are connected to Sx,
|
||||
// re-connect them here
|
||||
module->connect(SigSpec(wire, i), other_wire ? other_wire : SigSpec(RTLIL::Sx));
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
module->fixup_ports();
|
||||
design->add(module);
|
||||
|
||||
design->selection_stack.emplace_back(false);
|
||||
RTLIL::Selection& sel = design->selection_stack.back();
|
||||
sel.select(module);
|
||||
|
||||
Pass::call(design, "clean");
|
||||
|
||||
design->selection_stack.pop_back();
|
||||
|
||||
for (auto cell : module->cells().to_vector()) {
|
||||
if (cell->type != "$lut") continue;
|
||||
auto y_port = cell->getPort("\\Y").as_bit();
|
||||
if (y_port.wire->width == 1)
|
||||
module->rename(cell, stringf("%s$lut", y_port.wire->name.c_str()));
|
||||
else
|
||||
module->rename(cell, stringf("%s[%d]$lut", y_port.wire->name.c_str(), y_port.offset));
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -398,18 +1009,19 @@ struct AigerFrontend : public Frontend {
|
|||
log("Load module from an AIGER file into the current design.\n");
|
||||
log("\n");
|
||||
log(" -module_name <module_name>\n");
|
||||
log(" Name of module to be created (default: "
|
||||
#ifdef _WIN32
|
||||
"top" // FIXME
|
||||
#else
|
||||
"<filename>"
|
||||
#endif
|
||||
")\n");
|
||||
log(" Name of module to be created (default: <filename>)\n");
|
||||
log("\n");
|
||||
log(" -clk_name <wire_name>\n");
|
||||
log(" AIGER latches to be transformed into posedge DFFs clocked by wire of");
|
||||
log(" this name (default: clk)\n");
|
||||
log("\n");
|
||||
log(" -map <filename>\n");
|
||||
log(" read file with port and latch symbols\n");
|
||||
log("\n");
|
||||
log(" -wideports\n");
|
||||
log(" Merge ports that match the pattern 'name[int]' into a single\n");
|
||||
log(" multi-bit port 'name'.\n");
|
||||
log("\n");
|
||||
}
|
||||
void execute(std::istream *&f, std::string filename, std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
||||
{
|
||||
|
|
@ -417,6 +1029,8 @@ struct AigerFrontend : public Frontend {
|
|||
|
||||
RTLIL::IdString clk_name = "\\clk";
|
||||
RTLIL::IdString module_name;
|
||||
std::string map_filename;
|
||||
bool wideports = false;
|
||||
|
||||
size_t argidx;
|
||||
for (argidx = 1; argidx < args.size(); argidx++) {
|
||||
|
|
@ -429,13 +1043,23 @@ struct AigerFrontend : public Frontend {
|
|||
clk_name = RTLIL::escape_id(args[++argidx]);
|
||||
continue;
|
||||
}
|
||||
if (map_filename.empty() && arg == "-map" && argidx+1 < args.size()) {
|
||||
map_filename = args[++argidx];
|
||||
continue;
|
||||
}
|
||||
if (arg == "-wideports") {
|
||||
wideports = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(f, filename, args, argidx);
|
||||
|
||||
if (module_name.empty()) {
|
||||
#ifdef _WIN32
|
||||
module_name = "top"; // FIXME: basename equivalent on Win32?
|
||||
char fname[_MAX_FNAME];
|
||||
_splitpath(filename.c_str(), NULL /* drive */, NULL /* dir */, fname, NULL /* ext */)
|
||||
module_name = fname;
|
||||
#else
|
||||
char* bn = strdup(filename.c_str());
|
||||
module_name = RTLIL::escape_id(bn);
|
||||
|
|
@ -443,7 +1067,7 @@ struct AigerFrontend : public Frontend {
|
|||
#endif
|
||||
}
|
||||
|
||||
AigerReader reader(design, *f, module_name, clk_name);
|
||||
AigerReader reader(design, *f, module_name, clk_name, map_filename, wideports);
|
||||
reader.parse_aiger();
|
||||
}
|
||||
} AigerFrontend;
|
||||
|
|
|
|||
|
|
@ -2,7 +2,7 @@
|
|||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
|
||||
* Eddie Hung <eddie@fpgeh.com>
|
||||
* 2019 Eddie Hung <eddie@fpgeh.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
|
|
@ -31,20 +31,26 @@ struct AigerReader
|
|||
std::istream &f;
|
||||
RTLIL::IdString clk_name;
|
||||
RTLIL::Module *module;
|
||||
std::string map_filename;
|
||||
bool wideports;
|
||||
|
||||
unsigned M, I, L, O, A;
|
||||
unsigned B, C, J, F; // Optional in AIGER 1.9
|
||||
unsigned line_count;
|
||||
uint32_t piNum, flopNum;
|
||||
|
||||
std::vector<RTLIL::Wire*> inputs;
|
||||
std::vector<RTLIL::Wire*> latches;
|
||||
std::vector<RTLIL::Wire*> outputs;
|
||||
std::vector<RTLIL::Wire*> bad_properties;
|
||||
std::vector<RTLIL::Cell*> boxes;
|
||||
|
||||
AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name);
|
||||
AigerReader(RTLIL::Design *design, std::istream &f, RTLIL::IdString module_name, RTLIL::IdString clk_name, std::string map_filename, bool wideports);
|
||||
void parse_aiger();
|
||||
void parse_xaiger();
|
||||
void parse_aiger_ascii();
|
||||
void parse_aiger_binary();
|
||||
void post_process();
|
||||
};
|
||||
|
||||
YOSYS_NAMESPACE_END
|
||||
|
|
|
|||
|
|
@ -276,6 +276,18 @@ namespace RTLIL
|
|||
return std::string(c_str() + pos, len);
|
||||
}
|
||||
|
||||
bool begins_with(const char* prefix) const {
|
||||
size_t len = strlen(prefix);
|
||||
if (size() < len) return false;
|
||||
return substr(0, len) == prefix;
|
||||
}
|
||||
|
||||
bool ends_with(const char* suffix) const {
|
||||
size_t len = strlen(suffix);
|
||||
if (size() < len) return false;
|
||||
return substr(size()-len) == suffix;
|
||||
}
|
||||
|
||||
size_t size() const {
|
||||
return str().size();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -7,6 +7,7 @@ OBJS += passes/techmap/libparse.o
|
|||
|
||||
ifeq ($(ENABLE_ABC),1)
|
||||
OBJS += passes/techmap/abc.o
|
||||
OBJS += passes/techmap/abc9.o
|
||||
ifneq ($(ABCEXTERNAL),)
|
||||
passes/techmap/abc.o: CXXFLAGS += -DABCEXTERNAL='"$(ABCEXTERNAL)"'
|
||||
endif
|
||||
|
|
|
|||
|
|
@ -1453,7 +1453,7 @@ struct AbcPass : public Pass {
|
|||
log("internally. This is not going to \"run ABC on your design\". It will instead run\n");
|
||||
log("ABC on logic snippets extracted from your design. You will not get any useful\n");
|
||||
log("output when passing an ABC script that writes a file. Instead write your full\n");
|
||||
log("design as BLIF file with write_blif and the load that into ABC externally if\n");
|
||||
log("design as BLIF file with write_blif and then load that into ABC externally if\n");
|
||||
log("you want to use ABC to convert your design into another format.\n");
|
||||
log("\n");
|
||||
log("[1] http://www.eecs.berkeley.edu/~alanmi/abc/\n");
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
|
|
@ -75,13 +75,16 @@ struct SynthPass : public ScriptPass
|
|||
log(" from label is synonymous to 'begin', and empty to label is\n");
|
||||
log(" synonymous to the end of the command list.\n");
|
||||
log("\n");
|
||||
log(" -abc9\n");
|
||||
log(" use new ABC9 flow (EXPERIMENTAL)\n");
|
||||
log("\n");
|
||||
log("\n");
|
||||
log("The following commands are executed by this synthesis command:\n");
|
||||
help_script();
|
||||
log("\n");
|
||||
}
|
||||
|
||||
string top_module, fsm_opts, memory_opts;
|
||||
string top_module, fsm_opts, memory_opts, abc;
|
||||
bool autotop, flatten, noalumacc, nofsm, noabc, noshare;
|
||||
int lut;
|
||||
|
||||
|
|
@ -98,6 +101,7 @@ struct SynthPass : public ScriptPass
|
|||
nofsm = false;
|
||||
noabc = false;
|
||||
noshare = false;
|
||||
abc = "abc";
|
||||
}
|
||||
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
||||
|
|
@ -159,6 +163,10 @@ struct SynthPass : public ScriptPass
|
|||
noshare = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-abc9") {
|
||||
abc = "abc9";
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
|
@ -166,6 +174,9 @@ struct SynthPass : public ScriptPass
|
|||
if (!design->full_selection())
|
||||
log_cmd_error("This command only operates on fully selected designs!\n");
|
||||
|
||||
if (abc == "abc9" && !lut)
|
||||
log_cmd_error("ABC9 flow only supported for FPGA synthesis (using '-lut' option)");
|
||||
|
||||
log_header(design, "Executing SYNTH pass.\n");
|
||||
log_push();
|
||||
|
||||
|
|
@ -241,15 +252,15 @@ struct SynthPass : public ScriptPass
|
|||
#ifdef YOSYS_ENABLE_ABC
|
||||
if (help_mode)
|
||||
{
|
||||
run("abc -fast", " (unless -noabc, unless -lut)");
|
||||
run("abc -fast -lut k", "(unless -noabc, if -lut)");
|
||||
run(abc + " -fast", " (unless -noabc, unless -lut)");
|
||||
run(abc + " -fast -lut k", "(unless -noabc, if -lut)");
|
||||
}
|
||||
else
|
||||
{
|
||||
if (lut)
|
||||
run(stringf("abc -fast -lut %d", lut));
|
||||
run(stringf("%s -fast -lut %d", abc.c_str(), lut));
|
||||
else
|
||||
run("abc -fast");
|
||||
run(abc + " -fast");
|
||||
}
|
||||
run("opt -fast", " (unless -noabc)");
|
||||
#endif
|
||||
|
|
|
|||
|
|
@ -11,6 +11,9 @@ $(eval $(call add_share_file,share/ecp5,techlibs/ecp5/bram.txt))
|
|||
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/arith_map.v))
|
||||
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/latches_map.v))
|
||||
|
||||
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.box))
|
||||
$(eval $(call add_share_file,share/ecp5,techlibs/ecp5/abc_5g.lut))
|
||||
|
||||
EXTRA_OBJS += techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
|
||||
.SECONDARY: techlibs/ecp5/brams_init.mk techlibs/ecp5/brams_connect.mk
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,43 @@
|
|||
# NB: Inputs/Outputs must be ordered alphabetically
|
||||
# (with exceptions for carry in/out)
|
||||
|
||||
# Box 1 : CCU2C (2xCARRY + 2xLUT4)
|
||||
# Outputs: S0, S1, COUT
|
||||
# (NB: carry chain input/output must be last
|
||||
# input/output and bus has been moved
|
||||
# there overriding the otherwise
|
||||
# alphabetical ordering)
|
||||
# name ID w/b ins outs
|
||||
CCU2C 1 1 9 3
|
||||
|
||||
#A0 A1 B0 B1 C0 C1 D0 D1 CIN
|
||||
379 - 379 - 275 - 141 - 257
|
||||
630 379 630 379 526 275 392 141 273
|
||||
516 516 516 516 412 412 278 278 43
|
||||
|
||||
# Box 2 : TRELLIS_DPR16X4 (16x4 dist ram)
|
||||
# Outputs: DO0, DO1, DO2, DO3
|
||||
# name ID w/b ins outs
|
||||
TRELLIS_DPR16X4 2 0 14 4
|
||||
|
||||
#DI0 DI1 DI2 DI3 RAD0 RAD1 RAD2 RAD3 WAD0 WAD1 WAD2 WAD3 WCK WRE
|
||||
- - - - 141 379 275 379 - - - - - -
|
||||
- - - - 141 379 275 379 - - - - - -
|
||||
- - - - 141 379 275 379 - - - - - -
|
||||
- - - - 141 379 275 379 - - - - - -
|
||||
|
||||
# Box 3 : PFUMX (MUX2)
|
||||
# Outputs: Z
|
||||
# name ID w/b ins outs
|
||||
PFUMX 3 1 3 1
|
||||
|
||||
#ALUT BLUT C0
|
||||
98 98 151
|
||||
|
||||
# Box 4 : L6MUX21 (MUX2)
|
||||
# Outputs: Z
|
||||
# name ID w/b ins outs
|
||||
L6MUX21 4 1 3 1
|
||||
|
||||
#D0 D1 SD
|
||||
140 141 148
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
# ECP5-5G LUT library for ABC
|
||||
# Note that ECP5 architecture assigns difference
|
||||
# in LUT input delay to interconnect, so this is
|
||||
# considered too
|
||||
|
||||
|
||||
# Simple LUTs
|
||||
# area D C B A
|
||||
1 1 141
|
||||
2 1 141 275
|
||||
3 1 141 275 379
|
||||
4 1 141 275 379 379
|
||||
|
||||
# LUT5 = 2x LUT4 + PFUMX
|
||||
# area M0 D C B A
|
||||
5 2 151 239 373 477 477
|
||||
|
||||
# LUT6 = 2x LUT5 + MUX2
|
||||
# area M1 M0 D C B A
|
||||
6 4 148 292 380 514 618 618
|
||||
|
||||
# LUT7 = 2x LUT6 + MUX2
|
||||
# area M2 M1 M0 D C B A
|
||||
7 8 148 289 433 521 655 759 759
|
||||
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
# ECP5-5G LUT library for ABC
|
||||
# Note that ECP5 architecture assigns difference
|
||||
# in LUT input delay to interconnect, so this is
|
||||
# considered too
|
||||
|
||||
|
||||
# Simple LUTs
|
||||
# area D C B A
|
||||
1 1 141
|
||||
2 1 141 275
|
||||
3 1 141 275 379
|
||||
4 1 141 275 379 379
|
||||
|
|
@ -109,77 +109,102 @@ module \$lut (A, Y);
|
|||
input [WIDTH-1:0] A;
|
||||
output Y;
|
||||
|
||||
// Need to swap input ordering, and fix init accordingly,
|
||||
// to match ABC's expectation of LUT inputs in non-decreasing
|
||||
// delay order
|
||||
localparam P_WIDTH = WIDTH < 4 ? 4 : WIDTH;
|
||||
function [P_WIDTH-1:0] permute_index;
|
||||
input [P_WIDTH-1:0] i;
|
||||
integer j;
|
||||
begin
|
||||
permute_index = 0;
|
||||
for (j = 0; j < P_WIDTH; j = j + 1)
|
||||
permute_index[P_WIDTH-1 - j] = i[j];
|
||||
end
|
||||
endfunction
|
||||
|
||||
function [2**P_WIDTH-1:0] permute_init;
|
||||
integer i;
|
||||
begin
|
||||
permute_init = 0;
|
||||
for (i = 0; i < 2**P_WIDTH; i = i + 1)
|
||||
permute_init[i] = LUT[permute_index(i)];
|
||||
end
|
||||
endfunction
|
||||
|
||||
parameter [2**P_WIDTH-1:0] P_LUT = permute_init();
|
||||
|
||||
generate
|
||||
if (WIDTH == 1) begin
|
||||
LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y),
|
||||
.A(A[0]), .B(1'b0), .C(1'b0), .D(1'b0));
|
||||
LUT4 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.Z(Y),
|
||||
.A(1'b0), .B(1'b0), .C(1'b0), .D(A[0]));
|
||||
end else
|
||||
if (WIDTH == 2) begin
|
||||
LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y),
|
||||
.A(A[0]), .B(A[1]), .C(1'b0), .D(1'b0));
|
||||
LUT4 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.Z(Y),
|
||||
.A(1'b0), .B(1'b0), .C(A[1]), .D(A[0]));
|
||||
end else
|
||||
if (WIDTH == 3) begin
|
||||
LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(1'b0));
|
||||
LUT4 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.Z(Y),
|
||||
.A(1'b0), .B(A[2]), .C(A[1]), .D(A[0]));
|
||||
end else
|
||||
if (WIDTH == 4) begin
|
||||
LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.Z(Y),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
LUT4 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.Z(Y),
|
||||
.A(A[3]), .B(A[2]), .C(A[1]), .D(A[0]));
|
||||
`ifndef NO_PFUMUX
|
||||
end else
|
||||
if (WIDTH == 5) begin
|
||||
wire f0, f1;
|
||||
LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
PFUMX mux5(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(Y));
|
||||
LUT4 #(.INIT(P_LUT[15: 0])) lut0 (.Z(f0),
|
||||
.A(A[4]), .B(A[3]), .C(A[2]), .D(A[1]));
|
||||
LUT4 #(.INIT(P_LUT[31:16])) lut1 (.Z(f1),
|
||||
.A(A[4]), .B(A[3]), .C(A[2]), .D(A[1]));
|
||||
PFUMX mux5(.ALUT(f1), .BLUT(f0), .C0(A[0]), .Z(Y));
|
||||
end else
|
||||
if (WIDTH == 6) begin
|
||||
wire f0, f1, f2, f3, g0, g1;
|
||||
LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
LUT4 #(.INIT(P_LUT[15: 0])) lut0 (.Z(f0),
|
||||
.A(A[5]), .B(A[4]), .C(A[3]), .D(A[2]));
|
||||
LUT4 #(.INIT(P_LUT[31:16])) lut1 (.Z(f1),
|
||||
.A(A[5]), .B(A[4]), .C(A[3]), .D(A[2]));
|
||||
|
||||
LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
LUT4 #(.INIT(P_LUT[47:32])) lut2 (.Z(f2),
|
||||
.A(A[5]), .B(A[4]), .C(A[3]), .D(A[2]));
|
||||
LUT4 #(.INIT(P_LUT[63:48])) lut3 (.Z(f3),
|
||||
.A(A[5]), .B(A[4]), .C(A[3]), .D(A[2]));
|
||||
|
||||
PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0));
|
||||
PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1));
|
||||
L6MUX21 mux6 (.D0(g0), .D1(g1), .SD(A[5]), .Z(Y));
|
||||
PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[1]), .Z(g0));
|
||||
PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[1]), .Z(g1));
|
||||
L6MUX21 mux6 (.D0(g0), .D1(g1), .SD(A[0]), .Z(Y));
|
||||
end else
|
||||
if (WIDTH == 7) begin
|
||||
wire f0, f1, f2, f3, f4, f5, f6, f7, g0, g1, g2, g3, h0, h1;
|
||||
LUT4 #(.INIT(LUT[15: 0])) lut0 (.Z(f0),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
LUT4 #(.INIT(LUT[31:16])) lut1 (.Z(f1),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
LUT4 #(.INIT(P_LUT[15: 0])) lut0 (.Z(f0),
|
||||
.A(A[6]), .B(A[5]), .C(A[4]), .D(A[3]));
|
||||
LUT4 #(.INIT(P_LUT[31:16])) lut1 (.Z(f1),
|
||||
.A(A[6]), .B(A[5]), .C(A[4]), .D(A[3]));
|
||||
|
||||
LUT4 #(.INIT(LUT[47:32])) lut2 (.Z(f2),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
LUT4 #(.INIT(LUT[63:48])) lut3 (.Z(f3),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
LUT4 #(.INIT(P_LUT[47:32])) lut2 (.Z(f2),
|
||||
.A(A[6]), .B(A[5]), .C(A[4]), .D(A[3]));
|
||||
LUT4 #(.INIT(P_LUT[63:48])) lut3 (.Z(f3),
|
||||
.A(A[6]), .B(A[5]), .C(A[4]), .D(A[3]));
|
||||
|
||||
LUT4 #(.INIT(LUT[79:64])) lut4 (.Z(f4),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
LUT4 #(.INIT(LUT[95:80])) lut5 (.Z(f5),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
LUT4 #(.INIT(P_LUT[79:64])) lut4 (.Z(f4),
|
||||
.A(A[6]), .B(A[5]), .C(A[4]), .D(A[3]));
|
||||
LUT4 #(.INIT(P_LUT[95:80])) lut5 (.Z(f5),
|
||||
.A(A[6]), .B(A[5]), .C(A[4]), .D(A[3]));
|
||||
|
||||
LUT4 #(.INIT(LUT[111: 96])) lut6 (.Z(f6),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
LUT4 #(.INIT(LUT[127:112])) lut7 (.Z(f7),
|
||||
.A(A[0]), .B(A[1]), .C(A[2]), .D(A[3]));
|
||||
LUT4 #(.INIT(P_LUT[111: 96])) lut6 (.Z(f6),
|
||||
.A(A[6]), .B(A[5]), .C(A[4]), .D(A[3]));
|
||||
LUT4 #(.INIT(P_LUT[127:112])) lut7 (.Z(f7),
|
||||
.A(A[6]), .B(A[5]), .C(A[4]), .D(A[3]));
|
||||
|
||||
PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[4]), .Z(g0));
|
||||
PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[4]), .Z(g1));
|
||||
PFUMX mux52(.ALUT(f5), .BLUT(f4), .C0(A[4]), .Z(g2));
|
||||
PFUMX mux53(.ALUT(f7), .BLUT(f6), .C0(A[4]), .Z(g3));
|
||||
L6MUX21 mux60 (.D0(g0), .D1(g1), .SD(A[5]), .Z(h0));
|
||||
L6MUX21 mux61 (.D0(g2), .D1(g3), .SD(A[5]), .Z(h1));
|
||||
L6MUX21 mux7 (.D0(h0), .D1(h1), .SD(A[6]), .Z(Y));
|
||||
PFUMX mux50(.ALUT(f1), .BLUT(f0), .C0(A[2]), .Z(g0));
|
||||
PFUMX mux51(.ALUT(f3), .BLUT(f2), .C0(A[2]), .Z(g1));
|
||||
PFUMX mux52(.ALUT(f5), .BLUT(f4), .C0(A[2]), .Z(g2));
|
||||
PFUMX mux53(.ALUT(f7), .BLUT(f6), .C0(A[2]), .Z(g3));
|
||||
L6MUX21 mux60 (.D0(g0), .D1(g1), .SD(A[1]), .Z(h0));
|
||||
L6MUX21 mux61 (.D0(g2), .D1(g3), .SD(A[1]), .Z(h1));
|
||||
L6MUX21 mux7 (.D0(h0), .D1(h1), .SD(A[0]), .Z(Y));
|
||||
`endif
|
||||
end else begin
|
||||
wire _TECHMAP_FAIL_ = 1;
|
||||
|
|
|
|||
|
|
@ -9,13 +9,13 @@ module LUT4(input A, B, C, D, output Z);
|
|||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
|
||||
(* abc_box_id=4, lib_whitebox *)
|
||||
module L6MUX21 (input D0, D1, SD, output Z);
|
||||
assign Z = SD ? D1 : D0;
|
||||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
|
||||
(* abc_box_id=1, abc_carry="CIN,COUT", lib_whitebox *)
|
||||
module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1,
|
||||
output S0, S1, COUT);
|
||||
|
||||
|
|
@ -26,9 +26,13 @@ module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1,
|
|||
|
||||
// First half
|
||||
wire LUT4_0, LUT2_0;
|
||||
`ifdef _ABC
|
||||
assign LUT4_0 = INIT0[{D0, C0, B0, A0}];
|
||||
assign LUT2_0 = INIT0[{2'b00, B0, A0}];
|
||||
`else
|
||||
LUT4 #(.INIT(INIT0)) lut4_0(.A(A0), .B(B0), .C(C0), .D(D0), .Z(LUT4_0));
|
||||
LUT2 #(.INIT(INIT0[3:0])) lut2_0(.A(A0), .B(B0), .Z(LUT2_0));
|
||||
|
||||
`endif
|
||||
wire gated_cin_0 = (INJECT1_0 == "YES") ? 1'b0 : CIN;
|
||||
assign S0 = LUT4_0 ^ gated_cin_0;
|
||||
|
||||
|
|
@ -37,9 +41,13 @@ module CCU2C(input CIN, A0, B0, C0, D0, A1, B1, C1, D1,
|
|||
|
||||
// Second half
|
||||
wire LUT4_1, LUT2_1;
|
||||
`ifdef _ABC
|
||||
assign LUT4_1 = INIT1[{D1, C1, B1, A1}];
|
||||
assign LUT2_1 = INIT1[{2'b00, B1, A1}];
|
||||
`else
|
||||
LUT4 #(.INIT(INIT1)) lut4_1(.A(A1), .B(B1), .C(C1), .D(D1), .Z(LUT4_1));
|
||||
LUT2 #(.INIT(INIT1[3:0])) lut2_1(.A(A1), .B(B1), .Z(LUT2_1));
|
||||
|
||||
`endif
|
||||
wire gated_cin_1 = (INJECT1_1 == "YES") ? 1'b0 : cout_0;
|
||||
assign S1 = LUT4_1 ^ gated_cin_1;
|
||||
|
||||
|
|
@ -90,13 +98,13 @@ module TRELLIS_RAM16X2 (
|
|||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
|
||||
(* abc_box_id=3, lib_whitebox *)
|
||||
module PFUMX (input ALUT, BLUT, C0, output Z);
|
||||
assign Z = C0 ? ALUT : BLUT;
|
||||
endmodule
|
||||
|
||||
// ---------------------------------------
|
||||
|
||||
//(* abc_box_id=2, abc_scc_break="DI,WAD,WRE" *)
|
||||
module TRELLIS_DPR16X4 (
|
||||
input [3:0] DI,
|
||||
input [3:0] WAD,
|
||||
|
|
|
|||
|
|
@ -82,6 +82,9 @@ struct SynthEcp5Pass : public ScriptPass
|
|||
log(" -abc2\n");
|
||||
log(" run two passes of 'abc' for slightly improved logic density\n");
|
||||
log("\n");
|
||||
log(" -abc9\n");
|
||||
log(" use new ABC9 flow (EXPERIMENTAL)\n");
|
||||
log("\n");
|
||||
log(" -vpr\n");
|
||||
log(" generate an output netlist (and BLIF file) suitable for VPR\n");
|
||||
log(" (this feature is experimental and incomplete)\n");
|
||||
|
|
@ -93,7 +96,7 @@ struct SynthEcp5Pass : public ScriptPass
|
|||
}
|
||||
|
||||
string top_opt, blif_file, edif_file, json_file;
|
||||
bool noccu2, nodffe, nobram, nodram, nowidelut, flatten, retime, abc2, vpr;
|
||||
bool noccu2, nodffe, nobram, nodram, nowidelut, flatten, retime, abc2, abc9, vpr;
|
||||
|
||||
void clear_flags() YS_OVERRIDE
|
||||
{
|
||||
|
|
@ -110,6 +113,7 @@ struct SynthEcp5Pass : public ScriptPass
|
|||
retime = false;
|
||||
abc2 = false;
|
||||
vpr = false;
|
||||
abc9 = false;
|
||||
}
|
||||
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
||||
|
|
@ -184,6 +188,10 @@ struct SynthEcp5Pass : public ScriptPass
|
|||
vpr = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-abc9") {
|
||||
abc9 = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
|
@ -203,7 +211,7 @@ struct SynthEcp5Pass : public ScriptPass
|
|||
{
|
||||
if (check_label("begin"))
|
||||
{
|
||||
run("read_verilog -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
|
||||
run("read_verilog -D_ABC -lib +/ecp5/cells_sim.v +/ecp5/cells_bb.v");
|
||||
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
|
||||
}
|
||||
|
||||
|
|
@ -264,10 +272,17 @@ struct SynthEcp5Pass : public ScriptPass
|
|||
run("abc", " (only if -abc2)");
|
||||
}
|
||||
run("techmap -map +/ecp5/latches_map.v");
|
||||
if (nowidelut)
|
||||
run("abc -lut 4 -dress");
|
||||
else
|
||||
run("abc -lut 4:7 -dress");
|
||||
if (abc9) {
|
||||
if (nowidelut)
|
||||
run("abc9 -lut +/ecp5/abc_5g_nowide.lut -box +/ecp5/abc_5g.box -W 200");
|
||||
else
|
||||
run("abc9 -lut +/ecp5/abc_5g.lut -box +/ecp5/abc_5g.box -W 200");
|
||||
} else {
|
||||
if (nowidelut)
|
||||
run("abc -lut 4 -dress");
|
||||
else
|
||||
run("abc -lut 4:7 -dress");
|
||||
}
|
||||
run("clean");
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -28,6 +28,12 @@ $(eval $(call add_share_file,share/ice40,techlibs/ice40/cells_sim.v))
|
|||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/latches_map.v))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams.txt))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/brams_map.v))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.box))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_hx.lut))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_lp.box))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_lp.lut))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_u.box))
|
||||
$(eval $(call add_share_file,share/ice40,techlibs/ice40/abc_u.lut))
|
||||
|
||||
$(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init1.vh))
|
||||
$(eval $(call add_gen_share_file,share/ice40,techlibs/ice40/brams_init2.vh))
|
||||
|
|
|
|||
|
|
@ -0,0 +1,17 @@
|
|||
# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
|
||||
|
||||
# NB: Inputs/Outputs must be ordered alphabetically
|
||||
# (with exceptions for carry in/out)
|
||||
|
||||
# Inputs: I0 I1 CI
|
||||
# Outputs: CO
|
||||
# (NB: carry chain input/output must be last
|
||||
# input/output and have been moved there
|
||||
# overriding the alphabetical ordering)
|
||||
SB_CARRY 1 1 3 1
|
||||
259 231 126
|
||||
|
||||
# Inputs: I0 I1 I2 I3
|
||||
# Outputs: O
|
||||
SB_LUT4 2 1 4 1
|
||||
449 400 379 316
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_hx8k.txt
|
||||
# I3 I2 I1 I0
|
||||
1 1 316
|
||||
2 1 316 379
|
||||
3 1 316 379 400
|
||||
4 1 316 379 400 449
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
|
||||
|
||||
# NB: Inputs/Outputs must be ordered alphabetically
|
||||
# (with exceptions for carry in/out)
|
||||
|
||||
# Inputs: CI I0 I1
|
||||
# Outputs: CO
|
||||
# (NB: carry chain input/output must be last
|
||||
# input/output and have been moved there
|
||||
# overriding the alphabetical ordering)
|
||||
SB_CARRY 1 1 3 1
|
||||
675 609 186
|
||||
|
||||
# Inputs: I0 I1 I2 I3
|
||||
# Outputs: O
|
||||
SB_LUT4 2 1 4 1
|
||||
661 589 558 465
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_lp8k.txt
|
||||
# I3 I2 I1 I0
|
||||
1 1 465
|
||||
2 1 465 558
|
||||
3 1 465 558 589
|
||||
4 1 465 558 589 661
|
||||
|
|
@ -0,0 +1,17 @@
|
|||
# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
|
||||
|
||||
# NB: Inputs/Outputs must be ordered alphabetically
|
||||
# (with exceptions for carry in/out)
|
||||
|
||||
# Inputs: I0 I1 CI
|
||||
# Outputs: CO
|
||||
# (NB: carry chain input/output must be last
|
||||
# input/output and have been moved there
|
||||
# overriding the alphabetical ordering)
|
||||
SB_CARRY 1 1 3 1
|
||||
675 609 278
|
||||
|
||||
# Inputs: I0 I1 I2 I3
|
||||
# Outputs: O
|
||||
SB_LUT4 2 1 4 1
|
||||
1285 1231 1205 874
|
||||
|
|
@ -0,0 +1,6 @@
|
|||
# From https://github.com/cliffordwolf/icestorm/blob/be0bca0/icefuzz/timings_up5k.txt
|
||||
# I3 I2 I1 I0
|
||||
1 1 874
|
||||
2 1 874 1205
|
||||
3 1 874 1205 1231
|
||||
4 1 874 1205 1231 1285
|
||||
|
|
@ -37,20 +37,24 @@ module \$lut (A, Y);
|
|||
|
||||
generate
|
||||
if (WIDTH == 1) begin
|
||||
SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
|
||||
.I0(A[0]), .I1(1'b0), .I2(1'b0), .I3(1'b0));
|
||||
localparam [15:0] INIT = {{8{LUT[1]}}, {8{LUT[0]}}};
|
||||
SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y),
|
||||
.I0(1'b0), .I1(1'b0), .I2(1'b0), .I3(A[0]));
|
||||
end else
|
||||
if (WIDTH == 2) begin
|
||||
SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
|
||||
.I0(A[0]), .I1(A[1]), .I2(1'b0), .I3(1'b0));
|
||||
localparam [15:0] INIT = {{4{LUT[3]}}, {4{LUT[1]}}, {4{LUT[2]}}, {4{LUT[0]}}};
|
||||
SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y),
|
||||
.I0(1'b0), .I1(1'b0), .I2(A[1]), .I3(A[0]));
|
||||
end else
|
||||
if (WIDTH == 3) begin
|
||||
SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
|
||||
.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(1'b0));
|
||||
localparam [15:0] INIT = {{2{LUT[7]}}, {2{LUT[3]}}, {2{LUT[5]}}, {2{LUT[1]}}, {2{LUT[6]}}, {2{LUT[2]}}, {2{LUT[4]}}, {2{LUT[0]}}};
|
||||
SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y),
|
||||
.I0(1'b0), .I1(A[2]), .I2(A[1]), .I3(A[0]));
|
||||
end else
|
||||
if (WIDTH == 4) begin
|
||||
SB_LUT4 #(.LUT_INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
|
||||
.I0(A[0]), .I1(A[1]), .I2(A[2]), .I3(A[3]));
|
||||
localparam [15:0] INIT = {LUT[15], LUT[7], LUT[11], LUT[3], LUT[13], LUT[5], LUT[9], LUT[1], LUT[14], LUT[6], LUT[10], LUT[2], LUT[12], LUT[4], LUT[8], LUT[0]};
|
||||
SB_LUT4 #(.LUT_INIT(INIT)) _TECHMAP_REPLACE_ (.O(Y),
|
||||
.I0(A[3]), .I1(A[2]), .I2(A[1]), .I3(A[0]));
|
||||
end else begin
|
||||
wire _TECHMAP_FAIL_ = 1;
|
||||
end
|
||||
|
|
|
|||
|
|
@ -127,6 +127,7 @@ endmodule
|
|||
|
||||
// SiliconBlue Logic Cells
|
||||
|
||||
(* abc_box_id = 2, lib_whitebox *)
|
||||
module SB_LUT4 (output O, input I0, I1, I2, I3);
|
||||
parameter [15:0] LUT_INIT = 0;
|
||||
wire [7:0] s3 = I3 ? LUT_INIT[15:8] : LUT_INIT[7:0];
|
||||
|
|
@ -135,6 +136,7 @@ module SB_LUT4 (output O, input I0, I1, I2, I3);
|
|||
assign O = I0 ? s1[1] : s1[0];
|
||||
endmodule
|
||||
|
||||
(* abc_box_id = 1, abc_carry="CI,CO", lib_whitebox *)
|
||||
module SB_CARRY (output CO, input I0, I1, CI);
|
||||
assign CO = (I0 && I1) || ((I0 || I1) && CI);
|
||||
endmodule
|
||||
|
|
|
|||
|
|
@ -37,6 +37,10 @@ struct SynthIce40Pass : public ScriptPass
|
|||
log("\n");
|
||||
log("This command runs synthesis for iCE40 FPGAs.\n");
|
||||
log("\n");
|
||||
log(" -device < hx | lp | u >\n");
|
||||
log(" relevant only for '-abc9' flow, optimise timing for the specified device.\n");
|
||||
log(" default: hx\n");
|
||||
log("\n");
|
||||
log(" -top <module>\n");
|
||||
log(" use the specified module as top module\n");
|
||||
log("\n");
|
||||
|
|
@ -92,13 +96,16 @@ struct SynthIce40Pass : public ScriptPass
|
|||
log(" generate an output netlist (and BLIF file) suitable for VPR\n");
|
||||
log(" (this feature is experimental and incomplete)\n");
|
||||
log("\n");
|
||||
log(" -abc9\n");
|
||||
log(" use new ABC9 flow (EXPERIMENTAL)\n");
|
||||
log("\n");
|
||||
log("\n");
|
||||
log("The following commands are executed by this synthesis command:\n");
|
||||
help_script();
|
||||
log("\n");
|
||||
}
|
||||
|
||||
string top_opt, blif_file, edif_file, json_file;
|
||||
string top_opt, blif_file, edif_file, json_file, abc, device_opt;
|
||||
bool nocarry, nodffe, nobram, dsp, flatten, retime, relut, noabc, abc2, vpr;
|
||||
int min_ce_use;
|
||||
|
||||
|
|
@ -119,6 +126,8 @@ struct SynthIce40Pass : public ScriptPass
|
|||
noabc = false;
|
||||
abc2 = false;
|
||||
vpr = false;
|
||||
abc = "abc";
|
||||
device_opt = "hx";
|
||||
}
|
||||
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
||||
|
|
@ -201,12 +210,22 @@ struct SynthIce40Pass : public ScriptPass
|
|||
vpr = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-abc9") {
|
||||
abc = "abc9";
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-device" && argidx+1 < args.size()) {
|
||||
device_opt = args[++argidx];
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
||||
if (!design->full_selection())
|
||||
log_cmd_error("This command only operates on fully selected designs!\n");
|
||||
if (device_opt != "hx" && device_opt != "lp" && device_opt !="u")
|
||||
log_cmd_error("Invalid or no device specified: '%s'\n", device_opt.c_str());
|
||||
|
||||
log_header(design, "Executing SYNTH_ICE40 pass.\n");
|
||||
log_push();
|
||||
|
|
@ -220,7 +239,7 @@ struct SynthIce40Pass : public ScriptPass
|
|||
{
|
||||
if (check_label("begin"))
|
||||
{
|
||||
run("read_verilog -lib +/ice40/cells_sim.v");
|
||||
run("read_verilog -lib -D_ABC +/ice40/cells_sim.v");
|
||||
run(stringf("hierarchy -check %s", help_mode ? "-top <top>" : top_opt.c_str()));
|
||||
run("proc");
|
||||
}
|
||||
|
|
@ -277,8 +296,8 @@ struct SynthIce40Pass : public ScriptPass
|
|||
run("techmap");
|
||||
else
|
||||
run("techmap -map +/techmap.v -map +/ice40/arith_map.v");
|
||||
if (retime || help_mode)
|
||||
run("abc -dff", "(only if -retime)");
|
||||
if ((retime || help_mode) && abc != "abc9")
|
||||
run(abc + " -dff", "(only if -retime)");
|
||||
run("ice40_opt");
|
||||
}
|
||||
|
||||
|
|
@ -302,7 +321,7 @@ struct SynthIce40Pass : public ScriptPass
|
|||
if (check_label("map_luts"))
|
||||
{
|
||||
if (abc2 || help_mode) {
|
||||
run("abc", " (only if -abc2)");
|
||||
run(abc, " (only if -abc2)");
|
||||
run("ice40_opt", "(only if -abc2)");
|
||||
}
|
||||
run("techmap -map +/ice40/latches_map.v");
|
||||
|
|
@ -311,7 +330,18 @@ struct SynthIce40Pass : public ScriptPass
|
|||
run("techmap -map +/gate2lut.v -D LUT_WIDTH=4", "(only if -noabc)");
|
||||
}
|
||||
if (!noabc) {
|
||||
run("abc -dress -lut 4", "(skip if -noabc)");
|
||||
if (abc == "abc9") {
|
||||
int wire_delay;
|
||||
if (device_opt == "lp")
|
||||
wire_delay = 400;
|
||||
else if (device_opt == "u")
|
||||
wire_delay = 750;
|
||||
else
|
||||
wire_delay = 250;
|
||||
run(abc + stringf(" -W %d -lut +/ice40/abc_%s.lut -box +/ice40/abc_%s.box", wire_delay, device_opt.c_str(), device_opt.c_str()), "(skip if -noabc)");
|
||||
}
|
||||
else
|
||||
run(abc + " -dress -lut 4", "(skip if -noabc)");
|
||||
}
|
||||
run("clean");
|
||||
if (relut || help_mode) {
|
||||
|
|
|
|||
|
|
@ -30,6 +30,8 @@ $(eval $(call add_share_file,share/xilinx,techlibs/xilinx/drams_map.v))
|
|||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/arith_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/ff_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/lut_map.v))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.box))
|
||||
$(eval $(call add_share_file,share/xilinx,techlibs/xilinx/abc_xc7.lut))
|
||||
|
||||
$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_36.vh))
|
||||
$(eval $(call add_gen_share_file,share/xilinx,techlibs/xilinx/brams_init_32.vh))
|
||||
|
|
|
|||
|
|
@ -0,0 +1,53 @@
|
|||
# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/34ea6eb08a63d21ec16264ad37a0a7b142ff6031/artix7/timings/CLBLL_L.sdf
|
||||
|
||||
# NB: Inputs/Outputs must be ordered alphabetically
|
||||
# (with exceptions for carry in/out)
|
||||
|
||||
# F7BMUX slower than F7AMUX
|
||||
# Inputs: I0 I1 S0
|
||||
# Outputs: O
|
||||
F7BMUX 1 1 3 1
|
||||
217 223 296
|
||||
|
||||
# Inputs: I0 I1 S0
|
||||
# Outputs: O
|
||||
MUXF8 2 1 3 1
|
||||
104 94 273
|
||||
|
||||
# CARRY4 + CARRY4_[ABCD]X
|
||||
# Inputs: CYINIT DI0 DI1 DI2 DI3 S0 S1 S2 S3 CI
|
||||
# Outputs: O0 O1 O2 O3 CO0 CO1 CO2 CO3
|
||||
# (NB: carry chain input/output must be last
|
||||
# input/output and the entire bus has been
|
||||
# moved there overriding the otherwise
|
||||
# alphabetical ordering)
|
||||
CARRY4 3 1 10 8
|
||||
482 - - - - 223 - - - 222
|
||||
598 407 - - - 400 205 - - 334
|
||||
584 556 537 - - 523 558 226 - 239
|
||||
642 615 596 438 - 582 618 330 227 313
|
||||
536 379 - - - 340 - - - 271
|
||||
494 465 445 - - 433 469 - - 157
|
||||
592 540 520 356 - 512 548 292 - 228
|
||||
580 526 507 398 385 508 528 378 380 114
|
||||
|
||||
# SLICEM/A6LUT
|
||||
# Inputs: A0 A1 A2 A3 A4 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 WCLK WE
|
||||
# Outputs: DPO SPO
|
||||
RAM32X1D 4 0 13 2
|
||||
- - - - - - 631 472 407 238 127 - -
|
||||
631 472 407 238 127 - - - - - - - -
|
||||
|
||||
# SLICEM/A6LUT
|
||||
# Inputs: A0 A1 A2 A3 A4 A5 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 WCLK WE
|
||||
# Outputs: DPO SPO
|
||||
RAM64X1D 5 0 15 2
|
||||
- - - - - - - 642 631 472 407 238 127 - -
|
||||
642 631 472 407 238 127 - - - - - - - - -
|
||||
|
||||
# SLICEM/A6LUT + F7[AB]MUX
|
||||
# Inputs: A0 A1 A2 A3 A4 A5 A6 D DPRA0 DPRA1 DPRA2 DPRA3 DPRA4 DPRA5 DPRA6 WCLK WE
|
||||
# Outputs: DPO SPO
|
||||
RAM128X1D 6 0 17 2
|
||||
- - - - - - - - 1009 998 839 774 605 494 450 - -
|
||||
1047 1036 877 812 643 532 478 - - - - - - - - - -
|
||||
|
|
@ -0,0 +1,15 @@
|
|||
# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/82bf5f158cd8e9a11ac4d04f1aeef48ed1a528a5/artix7/timings/CLBLL_L.sdf
|
||||
# and https://github.com/SymbiFlow/prjxray-db/blob/82bf5f158cd8e9a11ac4d04f1aeef48ed1a528a5/artix7/tile_type_CLBLL_L.json
|
||||
|
||||
# K area delay
|
||||
1 1 127
|
||||
2 2 127 238
|
||||
3 3 127 238 407
|
||||
4 3 127 238 407 472
|
||||
5 3 127 238 407 472 631
|
||||
6 5 127 238 407 472 631 642
|
||||
# (F7[AB]MUX.S + [AC]OUTMUX) / 2
|
||||
7 10 464 513 624 793 858 1017 1028
|
||||
# F8MUX.S+BOUTMUX
|
||||
# F8MUX.I0+F7MUX.S+BOUTMUX
|
||||
8 20 468 585 634 745 914 979 1138 1149
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
# Max delays from https://github.com/SymbiFlow/prjxray-db/blob/82bf5f158cd8e9a11ac4d04f1aeef48ed1a528a5/artix7/timings/CLBLL_L.sdf
|
||||
# and https://github.com/SymbiFlow/prjxray-db/blob/82bf5f158cd8e9a11ac4d04f1aeef48ed1a528a5/artix7/tile_type_CLBLL_L.json
|
||||
|
||||
# K area delay
|
||||
1 1 127
|
||||
2 2 127 238
|
||||
3 3 127 238 407
|
||||
4 3 127 238 407 472
|
||||
5 3 127 238 407 472 631
|
||||
6 5 127 238 407 472 631 642
|
||||
|
|
@ -180,7 +180,7 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
|
|||
|
||||
// First one
|
||||
if (i == 0) begin
|
||||
CARRY4 #(.IS_INITIALIZED(1'd1)) carry4_1st_part
|
||||
CARRY4 carry4_1st_part
|
||||
(
|
||||
.CYINIT(CI),
|
||||
.CI (1'd0),
|
||||
|
|
@ -207,7 +207,7 @@ module _80_xilinx_alu (A, B, CI, BI, X, Y, CO);
|
|||
|
||||
// First one
|
||||
if (i == 0) begin
|
||||
CARRY4 #(.IS_INITIALIZED(1'd1)) carry4_1st_full
|
||||
CARRY4 carry4_1st_full
|
||||
(
|
||||
.CYINIT(CI),
|
||||
.CI (1'd0),
|
||||
|
|
|
|||
|
|
@ -2,6 +2,7 @@
|
|||
* yosys -- Yosys Open SYnthesis Suite
|
||||
*
|
||||
* Copyright (C) 2012 Clifford Wolf <clifford@clifford.at>
|
||||
* 2019 Eddie Hung <eddie@fpgeh.com>
|
||||
*
|
||||
* Permission to use, copy, modify, and/or distribute this software for any
|
||||
* purpose with or without fee is hereby granted, provided that the above
|
||||
|
|
@ -88,7 +89,7 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
|
|||
end else
|
||||
if (DEPTH > 65 && DEPTH <= 96) begin
|
||||
wire T0, T1, T2, T3, T4, T5, T6;
|
||||
SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
|
||||
SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
|
||||
SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
|
||||
\$__XILINX_SHREG_ #(.DEPTH(DEPTH-64), .INIT(INIT[DEPTH-64-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_2 (.C(C), .D(T3), .L(L[4:0]), .E(E), .Q(T4));
|
||||
if (&_TECHMAP_CONSTMSK_L_)
|
||||
|
|
@ -101,7 +102,7 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
|
|||
end else
|
||||
if (DEPTH > 97 && DEPTH < 128) begin
|
||||
wire T0, T1, T2, T3, T4, T5, T6, T7, T8;
|
||||
SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
|
||||
SRLC32E #(.INIT(INIT_R[32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
|
||||
SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
|
||||
SRLC32E #(.INIT(INIT_R[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
|
||||
\$__XILINX_SHREG_ #(.DEPTH(DEPTH-96), .INIT(INIT[DEPTH-96-1:0]), .CLKPOL(CLKPOL), .ENPOL(ENPOL)) fpga_srl_3 (.C(C), .D(T5), .L(L[4:0]), .E(E), .Q(T6));
|
||||
|
|
@ -115,9 +116,9 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
|
|||
end
|
||||
else if (DEPTH == 128) begin
|
||||
wire T0, T1, T2, T3, T4, T5, T6;
|
||||
SRLC32E #(.INIT(INIT_R[32-1:0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D(D), .Q(T0), .Q31(T1));
|
||||
SRLC32E #(.INIT(INIT_R[64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
|
||||
SRLC32E #(.INIT(INIT_R[96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
|
||||
SRLC32E #(.INIT(INIT_R[ 32-1: 0]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_0 (.A(L[4:0]), .CE(CE), .CLK(C), .D( D), .Q(T0), .Q31(T1));
|
||||
SRLC32E #(.INIT(INIT_R[ 64-1:32]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_1 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T1), .Q(T2), .Q31(T3));
|
||||
SRLC32E #(.INIT(INIT_R[ 96-1:64]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_2 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T3), .Q(T4), .Q31(T5));
|
||||
SRLC32E #(.INIT(INIT_R[128-1:96]), .IS_CLK_INVERTED(~CLKPOL[0])) fpga_srl_3 (.A(L[4:0]), .CE(CE), .CLK(C), .D(T5), .Q(T6), .Q31(SO));
|
||||
if (&_TECHMAP_CONSTMSK_L_)
|
||||
assign Q = T6;
|
||||
|
|
@ -151,6 +152,3 @@ module \$__XILINX_SHREG_ (input C, input D, input [31:0] L, input E, output Q, o
|
|||
end
|
||||
endgenerate
|
||||
endmodule
|
||||
|
||||
`ifndef SRL_ONLY
|
||||
`endif
|
||||
|
|
|
|||
|
|
@ -159,10 +159,12 @@ module MUXCY(output O, input CI, DI, S);
|
|||
assign O = S ? CI : DI;
|
||||
endmodule
|
||||
|
||||
(* abc_box_id = 1, lib_whitebox *)
|
||||
module MUXF7(output O, input I0, I1, S);
|
||||
assign O = S ? I1 : I0;
|
||||
endmodule
|
||||
|
||||
(* abc_box_id = 2, lib_whitebox *)
|
||||
module MUXF8(output O, input I0, I1, S);
|
||||
assign O = S ? I1 : I0;
|
||||
endmodule
|
||||
|
|
@ -171,6 +173,7 @@ module XORCY(output O, input CI, LI);
|
|||
assign O = CI ^ LI;
|
||||
endmodule
|
||||
|
||||
(* abc_box_id = 3, abc_carry="CI,CO", lib_whitebox *)
|
||||
module CARRY4(output [3:0] CO, O, input CI, CYINIT, input [3:0] DI, S);
|
||||
assign O = S ^ {CO[2:0], CI | CYINIT};
|
||||
assign CO[0] = S[0] ? CI | CYINIT : DI[0];
|
||||
|
|
@ -278,6 +281,7 @@ module FDPE_1 (output reg Q, input C, CE, D, PRE);
|
|||
always @(negedge C, posedge PRE) if (PRE) Q <= 1'b1; else if (CE) Q <= D;
|
||||
endmodule
|
||||
|
||||
(* abc_box_id = 4, abc_scc_break="D,WE" *)
|
||||
module RAM32X1D (
|
||||
output DPO, SPO,
|
||||
input D, WCLK, WE,
|
||||
|
|
@ -295,6 +299,7 @@ module RAM32X1D (
|
|||
always @(posedge clk) if (WE) mem[a] <= D;
|
||||
endmodule
|
||||
|
||||
(* abc_box_id = 5, abc_scc_break="D,WE" *)
|
||||
module RAM64X1D (
|
||||
output DPO, SPO,
|
||||
input D, WCLK, WE,
|
||||
|
|
@ -312,6 +317,7 @@ module RAM64X1D (
|
|||
always @(posedge clk) if (WE) mem[a] <= D;
|
||||
endmodule
|
||||
|
||||
(* abc_box_id = 6, abc_scc_break="D,WE" *)
|
||||
module RAM128X1D (
|
||||
output DPO, SPO,
|
||||
input D, WCLK, WE,
|
||||
|
|
|
|||
|
|
@ -125,7 +125,7 @@ function xtract_cell_decl()
|
|||
xtract_cell_decl RAM32X1S_1
|
||||
xtract_cell_decl RAM32X2S
|
||||
xtract_cell_decl RAM64M
|
||||
xtract_cell_decl RAM64X1D
|
||||
#xtract_cell_decl RAM64X1D
|
||||
xtract_cell_decl RAM64X1S
|
||||
xtract_cell_decl RAM64X1S_1
|
||||
xtract_cell_decl RAM64X2S
|
||||
|
|
|
|||
|
|
@ -3738,13 +3738,6 @@ module RAM64M (...);
|
|||
input WE;
|
||||
endmodule
|
||||
|
||||
module RAM64X1D (...);
|
||||
parameter [63:0] INIT = 64'h0000000000000000;
|
||||
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
|
||||
output DPO, SPO;
|
||||
input A0, A1, A2, A3, A4, A5, D, DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5, WCLK, WE;
|
||||
endmodule
|
||||
|
||||
module RAM64X1S (...);
|
||||
parameter [63:0] INIT = 64'h0000000000000000;
|
||||
parameter [0:0] IS_WCLK_INVERTED = 1'b0;
|
||||
|
|
|
|||
|
|
@ -29,61 +29,86 @@ module \$lut (A, Y);
|
|||
input [WIDTH-1:0] A;
|
||||
output Y;
|
||||
|
||||
// Need to swap input ordering, and fix init accordingly,
|
||||
// to match ABC's expectation of LUT inputs in non-decreasing
|
||||
// delay order
|
||||
function [WIDTH-1:0] permute_index;
|
||||
input [WIDTH-1:0] i;
|
||||
integer j;
|
||||
begin
|
||||
permute_index = 0;
|
||||
for (j = 0; j < WIDTH; j = j + 1)
|
||||
permute_index[WIDTH-1 - j] = i[j];
|
||||
end
|
||||
endfunction
|
||||
|
||||
function [2**WIDTH-1:0] permute_init;
|
||||
input [2**WIDTH-1:0] orig;
|
||||
integer i;
|
||||
begin
|
||||
permute_init = 0;
|
||||
for (i = 0; i < 2**WIDTH; i = i + 1)
|
||||
permute_init[i] = orig[permute_index(i)];
|
||||
end
|
||||
endfunction
|
||||
|
||||
parameter [2**WIDTH-1:0] P_LUT = permute_init(LUT);
|
||||
|
||||
generate
|
||||
if (WIDTH == 1) begin
|
||||
LUT1 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
|
||||
LUT1 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
|
||||
.I0(A[0]));
|
||||
end else
|
||||
if (WIDTH == 2) begin
|
||||
LUT2 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
|
||||
.I0(A[0]), .I1(A[1]));
|
||||
LUT2 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
|
||||
.I0(A[1]), .I1(A[0]));
|
||||
end else
|
||||
if (WIDTH == 3) begin
|
||||
LUT3 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
|
||||
.I0(A[0]), .I1(A[1]), .I2(A[2]));
|
||||
LUT3 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
|
||||
.I0(A[2]), .I1(A[1]), .I2(A[0]));
|
||||
end else
|
||||
if (WIDTH == 4) begin
|
||||
LUT4 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
|
||||
.I0(A[0]), .I1(A[1]), .I2(A[2]),
|
||||
.I3(A[3]));
|
||||
LUT4 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
|
||||
.I0(A[3]), .I1(A[2]), .I2(A[1]),
|
||||
.I3(A[0]));
|
||||
end else
|
||||
if (WIDTH == 5) begin
|
||||
LUT5 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
|
||||
.I0(A[0]), .I1(A[1]), .I2(A[2]),
|
||||
.I3(A[3]), .I4(A[4]));
|
||||
LUT5 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
|
||||
.I0(A[4]), .I1(A[3]), .I2(A[2]),
|
||||
.I3(A[1]), .I4(A[0]));
|
||||
end else
|
||||
if (WIDTH == 6) begin
|
||||
LUT6 #(.INIT(LUT)) _TECHMAP_REPLACE_ (.O(Y),
|
||||
.I0(A[0]), .I1(A[1]), .I2(A[2]),
|
||||
.I3(A[3]), .I4(A[4]), .I5(A[5]));
|
||||
LUT6 #(.INIT(P_LUT)) _TECHMAP_REPLACE_ (.O(Y),
|
||||
.I0(A[5]), .I1(A[4]), .I2(A[3]),
|
||||
.I3(A[2]), .I4(A[1]), .I5(A[0]));
|
||||
end else
|
||||
if (WIDTH == 7) begin
|
||||
wire T0, T1;
|
||||
LUT6 #(.INIT(LUT[63:0])) fpga_lut_0 (.O(T0),
|
||||
.I0(A[0]), .I1(A[1]), .I2(A[2]),
|
||||
.I3(A[3]), .I4(A[4]), .I5(A[5]));
|
||||
LUT6 #(.INIT(LUT[127:64])) fpga_lut_1 (.O(T1),
|
||||
.I0(A[0]), .I1(A[1]), .I2(A[2]),
|
||||
.I3(A[3]), .I4(A[4]), .I5(A[5]));
|
||||
MUXF7 fpga_mux_0 (.O(Y), .I0(T0), .I1(T1), .S(A[6]));
|
||||
LUT6 #(.INIT(P_LUT[63:0])) fpga_lut_0 (.O(T0),
|
||||
.I0(A[6]), .I1(A[5]), .I2(A[4]),
|
||||
.I3(A[3]), .I4(A[2]), .I5(A[1]));
|
||||
LUT6 #(.INIT(P_LUT[127:64])) fpga_lut_1 (.O(T1),
|
||||
.I0(A[6]), .I1(A[5]), .I2(A[4]),
|
||||
.I3(A[3]), .I4(A[2]), .I5(A[1]));
|
||||
MUXF7 fpga_mux_0 (.O(Y), .I0(T0), .I1(T1), .S(A[0]));
|
||||
end else
|
||||
if (WIDTH == 8) begin
|
||||
wire T0, T1, T2, T3, T4, T5;
|
||||
LUT6 #(.INIT(LUT[63:0])) fpga_lut_0 (.O(T0),
|
||||
.I0(A[0]), .I1(A[1]), .I2(A[2]),
|
||||
.I3(A[3]), .I4(A[4]), .I5(A[5]));
|
||||
LUT6 #(.INIT(LUT[127:64])) fpga_lut_1 (.O(T1),
|
||||
.I0(A[0]), .I1(A[1]), .I2(A[2]),
|
||||
.I3(A[3]), .I4(A[4]), .I5(A[5]));
|
||||
LUT6 #(.INIT(LUT[191:128])) fpga_lut_2 (.O(T2),
|
||||
.I0(A[0]), .I1(A[1]), .I2(A[2]),
|
||||
.I3(A[3]), .I4(A[4]), .I5(A[5]));
|
||||
LUT6 #(.INIT(LUT[255:192])) fpga_lut_3 (.O(T3),
|
||||
.I0(A[0]), .I1(A[1]), .I2(A[2]),
|
||||
.I3(A[3]), .I4(A[4]), .I5(A[5]));
|
||||
MUXF7 fpga_mux_0 (.O(T4), .I0(T0), .I1(T1), .S(A[6]));
|
||||
MUXF7 fpga_mux_1 (.O(T5), .I0(T2), .I1(T3), .S(A[6]));
|
||||
MUXF8 fpga_mux_2 (.O(Y), .I0(T4), .I1(T5), .S(A[7]));
|
||||
LUT6 #(.INIT(P_LUT[63:0])) fpga_lut_0 (.O(T0),
|
||||
.I0(A[7]), .I1(A[6]), .I2(A[5]),
|
||||
.I3(A[4]), .I4(A[3]), .I5(A[2]));
|
||||
LUT6 #(.INIT(P_LUT[127:64])) fpga_lut_1 (.O(T1),
|
||||
.I0(A[7]), .I1(A[6]), .I2(A[5]),
|
||||
.I3(A[4]), .I4(A[3]), .I5(A[2]));
|
||||
LUT6 #(.INIT(P_LUT[191:128])) fpga_lut_2 (.O(T2),
|
||||
.I0(A[7]), .I1(A[6]), .I2(A[5]),
|
||||
.I3(A[4]), .I4(A[3]), .I5(A[2]));
|
||||
LUT6 #(.INIT(P_LUT[255:192])) fpga_lut_3 (.O(T3),
|
||||
.I0(A[7]), .I1(A[6]), .I2(A[5]),
|
||||
.I3(A[4]), .I4(A[3]), .I5(A[2]));
|
||||
MUXF7 fpga_mux_0 (.O(T4), .I0(T0), .I1(T1), .S(A[1]));
|
||||
MUXF7 fpga_mux_1 (.O(T5), .I0(T2), .I1(T3), .S(A[1]));
|
||||
MUXF8 fpga_mux_2 (.O(Y), .I0(T4), .I1(T5), .S(A[0]));
|
||||
end else begin
|
||||
wire _TECHMAP_FAIL_ = 1;
|
||||
end
|
||||
|
|
|
|||
|
|
@ -25,6 +25,9 @@
|
|||
USING_YOSYS_NAMESPACE
|
||||
PRIVATE_NAMESPACE_BEGIN
|
||||
|
||||
#define XC7_WIRE_DELAY "300" // Number with which ABC will map a 6-input gate
|
||||
// to one LUT6 (instead of a LUT5 + LUT2)
|
||||
|
||||
struct SynthXilinxPass : public ScriptPass
|
||||
{
|
||||
SynthXilinxPass() : ScriptPass("synth_xilinx", "synthesis for Xilinx FPGAs") { }
|
||||
|
|
@ -85,6 +88,9 @@ struct SynthXilinxPass : public ScriptPass
|
|||
log(" -retime\n");
|
||||
log(" run 'abc' with -dff option\n");
|
||||
log("\n");
|
||||
log(" -abc9\n");
|
||||
log(" use new ABC9 flow (EXPERIMENTAL)\n");
|
||||
log("\n");
|
||||
log("\n");
|
||||
log("The following commands are executed by this synthesis command:\n");
|
||||
help_script();
|
||||
|
|
@ -92,22 +98,24 @@ struct SynthXilinxPass : public ScriptPass
|
|||
}
|
||||
|
||||
std::string top_opt, edif_file, blif_file, family;
|
||||
bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut;
|
||||
bool flatten, retime, vpr, nobram, nodram, nosrl, nocarry, nowidelut, abc9;
|
||||
|
||||
void clear_flags() YS_OVERRIDE
|
||||
{
|
||||
top_opt = "-auto-top";
|
||||
edif_file.clear();
|
||||
blif_file.clear();
|
||||
family = "xc7";
|
||||
flatten = false;
|
||||
retime = false;
|
||||
vpr = false;
|
||||
nocarry = false;
|
||||
nobram = false;
|
||||
nodram = false;
|
||||
nosrl = false;
|
||||
nocarry = false;
|
||||
nowidelut = false;
|
||||
family = "xc7";
|
||||
abc9 = false;
|
||||
}
|
||||
|
||||
void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
|
||||
|
|
@ -162,6 +170,10 @@ struct SynthXilinxPass : public ScriptPass
|
|||
vpr = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nocarry") {
|
||||
nocarry = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-nobram") {
|
||||
nobram = true;
|
||||
continue;
|
||||
|
|
@ -174,6 +186,10 @@ struct SynthXilinxPass : public ScriptPass
|
|||
nosrl = true;
|
||||
continue;
|
||||
}
|
||||
if (args[argidx] == "-abc9") {
|
||||
abc9 = true;
|
||||
continue;
|
||||
}
|
||||
break;
|
||||
}
|
||||
extra_args(args, argidx, design);
|
||||
|
|
@ -196,9 +212,9 @@ struct SynthXilinxPass : public ScriptPass
|
|||
{
|
||||
if (check_label("begin")) {
|
||||
if (vpr)
|
||||
run("read_verilog -lib -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
|
||||
run("read_verilog -lib -D _ABC -D_EXPLICIT_CARRY +/xilinx/cells_sim.v");
|
||||
else
|
||||
run("read_verilog -lib +/xilinx/cells_sim.v");
|
||||
run("read_verilog -lib -D _ABC +/xilinx/cells_sim.v");
|
||||
|
||||
run("read_verilog -lib +/xilinx/cells_xtra.v");
|
||||
|
||||
|
|
@ -217,6 +233,17 @@ struct SynthXilinxPass : public ScriptPass
|
|||
|
||||
if (check_label("coarse")) {
|
||||
run("synth -run coarse");
|
||||
|
||||
// shregmap -tech xilinx can cope with $shiftx and $mux
|
||||
// cells for identifying variable-length shift registers,
|
||||
// so attempt to convert $pmux-es to the former
|
||||
if (!nosrl || help_mode)
|
||||
run("pmux2shiftx", "(skip if '-nosrl')");
|
||||
|
||||
// Run a number of peephole optimisations, including one
|
||||
// that optimises $mul cells driving $shiftx's B input
|
||||
// and that aids wide mux analysis
|
||||
run("peepopt");
|
||||
}
|
||||
|
||||
if (check_label("bram", "(skip if '-nobram')")) {
|
||||
|
|
@ -234,12 +261,6 @@ struct SynthXilinxPass : public ScriptPass
|
|||
}
|
||||
|
||||
if (check_label("fine")) {
|
||||
// shregmap -tech xilinx can cope with $shiftx and $mux
|
||||
// cells for identifiying variable-length shift registers,
|
||||
// so attempt to convert $pmux-es to the former
|
||||
if (!nosrl || help_mode)
|
||||
run("pmux2shiftx", "(skip if '-nosrl')");
|
||||
|
||||
run("opt -fast -full");
|
||||
run("memory_map");
|
||||
run("dffsr2dff");
|
||||
|
|
@ -254,15 +275,17 @@ struct SynthXilinxPass : public ScriptPass
|
|||
run("shregmap -tech xilinx -minlen 3", "(skip if '-nosrl')");
|
||||
}
|
||||
|
||||
std::string techmap_files = " -map +/techmap.v";
|
||||
if (help_mode)
|
||||
run("techmap -map +/techmap.v [-map +/xilinx/arith_map.v]", "(skip if '-nocarry')");
|
||||
techmap_files += " [-map +/xilinx/arith_map.v]";
|
||||
else if (!nocarry) {
|
||||
if (!vpr)
|
||||
run("techmap -map +/techmap.v -map +/xilinx/arith_map.v");
|
||||
else
|
||||
run("techmap -map +/techmap.v -map +/xilinx/arith_map.v -D _EXPLICIT_CARRY");
|
||||
techmap_files += " -map +/xilinx/arith_map.v";
|
||||
if (vpr)
|
||||
techmap_files += " -D _EXPLICIT_CARRY";
|
||||
else if (abc9)
|
||||
techmap_files += " -D _CLB_CARRY";
|
||||
}
|
||||
|
||||
run("techmap " + techmap_files);
|
||||
run("opt -fast");
|
||||
}
|
||||
|
||||
|
|
@ -272,13 +295,25 @@ struct SynthXilinxPass : public ScriptPass
|
|||
}
|
||||
|
||||
if (check_label("map_luts")) {
|
||||
run("opt_expr -mux_undef");
|
||||
if (help_mode)
|
||||
run("abc -luts 2:2,3,6:5[,10,20] [-dff]", "(skip if 'nowidelut', only for '-retime')");
|
||||
else if (nowidelut)
|
||||
run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
|
||||
else
|
||||
run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
|
||||
else if (abc9) {
|
||||
if (family != "xc7")
|
||||
log_warning("'synth_xilinx -abc9' currently supports '-family xc7' only.\n");
|
||||
if (nowidelut)
|
||||
run("abc9 -lut +/xilinx/abc_xc7_nowide.lut -box +/xilinx/abc_xc7.box -W " + std::string(XC7_WIRE_DELAY) + string(retime ? " -dff" : ""));
|
||||
else
|
||||
run("abc9 -lut +/xilinx/abc_xc7.lut -box +/xilinx/abc_xc7.box -W " + std::string(XC7_WIRE_DELAY) + string(retime ? " -dff" : ""));
|
||||
}
|
||||
else {
|
||||
if (nowidelut)
|
||||
run("abc -luts 2:2,3,6:5" + string(retime ? " -dff" : ""));
|
||||
else
|
||||
run("abc -luts 2:2,3,6:5,10,20" + string(retime ? " -dff" : ""));
|
||||
}
|
||||
run("clean");
|
||||
|
||||
// This shregmap call infers fixed length shift registers after abc
|
||||
// has performed any necessary retiming
|
||||
if (!nosrl || help_mode)
|
||||
|
|
|
|||
|
|
@ -0,0 +1,2 @@
|
|||
MUXF8 1 0 3 1
|
||||
1 1 1
|
||||
|
|
@ -0,0 +1,269 @@
|
|||
module abc9_test001(input a, output o);
|
||||
assign o = a;
|
||||
endmodule
|
||||
|
||||
module abc9_test002(input [1:0] a, output o);
|
||||
assign o = a[1];
|
||||
endmodule
|
||||
|
||||
module abc9_test003(input [1:0] a, output [1:0] o);
|
||||
assign o = a;
|
||||
endmodule
|
||||
|
||||
module abc9_test004(input [1:0] a, output o);
|
||||
assign o = ^a;
|
||||
endmodule
|
||||
|
||||
module abc9_test005(input [1:0] a, output o, output p);
|
||||
assign o = ^a;
|
||||
assign p = ~o;
|
||||
endmodule
|
||||
|
||||
module abc9_test006(input [1:0] a, output [2:0] o);
|
||||
assign o[0] = ^a;
|
||||
assign o[1] = ~o[0];
|
||||
assign o[2] = o[1];
|
||||
endmodule
|
||||
|
||||
module abc9_test007(input a, output o);
|
||||
wire b, c;
|
||||
assign c = ~a;
|
||||
assign b = c;
|
||||
abc9_test007_sub s(b, o);
|
||||
endmodule
|
||||
|
||||
module abc9_test007_sub(input a, output b);
|
||||
assign b = a;
|
||||
endmodule
|
||||
|
||||
module abc9_test008(input a, output o);
|
||||
wire b, c;
|
||||
assign b = ~a;
|
||||
assign c = b;
|
||||
abc9_test008_sub s(b, o);
|
||||
endmodule
|
||||
|
||||
module abc9_test008_sub(input a, output b);
|
||||
assign b = ~a;
|
||||
endmodule
|
||||
|
||||
module abc9_test009(inout io, input oe);
|
||||
reg latch;
|
||||
always @(io or oe)
|
||||
if (!oe)
|
||||
latch <= io;
|
||||
assign io = oe ? ~latch : 1'bz;
|
||||
endmodule
|
||||
|
||||
module abc9_test010(inout [7:0] io, input oe);
|
||||
reg [7:0] latch;
|
||||
always @(io or oe)
|
||||
if (!oe)
|
||||
latch <= io;
|
||||
assign io = oe ? ~latch : 8'bz;
|
||||
endmodule
|
||||
|
||||
module abc9_test011(inout io, input oe);
|
||||
reg latch;
|
||||
always @(io or oe)
|
||||
if (!oe)
|
||||
latch <= io;
|
||||
//assign io = oe ? ~latch : 8'bz;
|
||||
endmodule
|
||||
|
||||
module abc9_test012(inout io, input oe);
|
||||
reg latch;
|
||||
//always @(io or oe)
|
||||
// if (!oe)
|
||||
// latch <= io;
|
||||
assign io = oe ? ~latch : 8'bz;
|
||||
endmodule
|
||||
|
||||
module abc9_test013(inout [3:0] io, input oe);
|
||||
reg [3:0] latch;
|
||||
always @(io or oe)
|
||||
if (!oe)
|
||||
latch[3:0] <= io[3:0];
|
||||
else
|
||||
latch[7:4] <= io;
|
||||
assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
|
||||
assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
|
||||
endmodule
|
||||
|
||||
module abc9_test014(inout [7:0] io, input oe);
|
||||
abc9_test012_sub sub(io, oe);
|
||||
endmodule
|
||||
|
||||
module abc9_test012_sub(inout [7:0] io, input oe);
|
||||
reg [7:0] latch;
|
||||
always @(io or oe)
|
||||
if (!oe)
|
||||
latch[3:0] <= io;
|
||||
else
|
||||
latch[7:4] <= io;
|
||||
assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
|
||||
assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
|
||||
endmodule
|
||||
|
||||
module abc9_test015(input a, output b, input c);
|
||||
assign b = ~a;
|
||||
(* keep *) wire d;
|
||||
assign d = ~c;
|
||||
endmodule
|
||||
|
||||
module abc9_test016(input a, output b);
|
||||
assign b = ~a;
|
||||
(* keep *) reg c;
|
||||
always @* c <= ~a;
|
||||
endmodule
|
||||
|
||||
module abc9_test017(input a, output b);
|
||||
assign b = ~a;
|
||||
(* keep *) reg c;
|
||||
always @* c = b;
|
||||
endmodule
|
||||
|
||||
module abc9_test018(input a, output b, output c);
|
||||
assign b = ~a;
|
||||
(* keep *) wire [1:0] d;
|
||||
assign c = &d;
|
||||
endmodule
|
||||
|
||||
module abc9_test019(input a, output b);
|
||||
assign b = ~a;
|
||||
(* keep *) reg [1:0] c;
|
||||
reg d;
|
||||
always @* d <= &c;
|
||||
endmodule
|
||||
|
||||
module abc9_test020(input a, output b);
|
||||
assign b = ~a;
|
||||
(* keep *) reg [1:0] c;
|
||||
(* keep *) reg d;
|
||||
always @* d <= &c;
|
||||
endmodule
|
||||
|
||||
// Citation: https://github.com/alexforencich/verilog-ethernet
|
||||
module abc9_test021(clk, rst, s_eth_hdr_valid, s_eth_hdr_ready, s_eth_dest_mac, s_eth_src_mac, s_eth_type, s_eth_payload_axis_tdata, s_eth_payload_axis_tkeep, s_eth_payload_axis_tvalid, s_eth_payload_axis_tready, s_eth_payload_axis_tlast, s_eth_payload_axis_tid, s_eth_payload_axis_tdest, s_eth_payload_axis_tuser, m_eth_hdr_valid, m_eth_hdr_ready, m_eth_dest_mac, m_eth_src_mac, m_eth_type, m_eth_payload_axis_tdata, m_eth_payload_axis_tkeep, m_eth_payload_axis_tvalid, m_eth_payload_axis_tready, m_eth_payload_axis_tlast, m_eth_payload_axis_tid, m_eth_payload_axis_tdest, m_eth_payload_axis_tuser);
|
||||
input clk;
|
||||
output [47:0] m_eth_dest_mac;
|
||||
input m_eth_hdr_ready;
|
||||
output m_eth_hdr_valid;
|
||||
output [7:0] m_eth_payload_axis_tdata;
|
||||
output [7:0] m_eth_payload_axis_tdest;
|
||||
output [7:0] m_eth_payload_axis_tid;
|
||||
output m_eth_payload_axis_tkeep;
|
||||
output m_eth_payload_axis_tlast;
|
||||
input m_eth_payload_axis_tready;
|
||||
output m_eth_payload_axis_tuser;
|
||||
output m_eth_payload_axis_tvalid;
|
||||
output [47:0] m_eth_src_mac;
|
||||
output [15:0] m_eth_type;
|
||||
input rst;
|
||||
input [191:0] s_eth_dest_mac;
|
||||
output [3:0] s_eth_hdr_ready;
|
||||
input [3:0] s_eth_hdr_valid;
|
||||
input [31:0] s_eth_payload_axis_tdata;
|
||||
input [31:0] s_eth_payload_axis_tdest;
|
||||
input [31:0] s_eth_payload_axis_tid;
|
||||
input [3:0] s_eth_payload_axis_tkeep;
|
||||
input [3:0] s_eth_payload_axis_tlast;
|
||||
output [3:0] s_eth_payload_axis_tready;
|
||||
input [3:0] s_eth_payload_axis_tuser;
|
||||
input [3:0] s_eth_payload_axis_tvalid;
|
||||
input [191:0] s_eth_src_mac;
|
||||
input [63:0] s_eth_type;
|
||||
(* keep *)
|
||||
wire [0:0] grant, request;
|
||||
wire a;
|
||||
not u0 (
|
||||
a,
|
||||
grant[0]
|
||||
);
|
||||
and u1 (
|
||||
request[0],
|
||||
s_eth_hdr_valid[0],
|
||||
a
|
||||
);
|
||||
(* keep *)
|
||||
MUXF8 u2 (
|
||||
.I0(1'bx),
|
||||
.I1(1'bx),
|
||||
.O(o),
|
||||
.S(1'bx)
|
||||
);
|
||||
arbiter arb_inst (
|
||||
.acknowledge(acknowledge),
|
||||
.clk(clk),
|
||||
.grant(grant),
|
||||
.grant_encoded(grant_encoded),
|
||||
.grant_valid(grant_valid),
|
||||
.request(request),
|
||||
.rst(rst)
|
||||
);
|
||||
endmodule
|
||||
|
||||
module arbiter (clk, rst, request, acknowledge, grant, grant_valid, grant_encoded);
|
||||
input [3:0] acknowledge;
|
||||
input clk;
|
||||
output [3:0] grant;
|
||||
output [1:0] grant_encoded;
|
||||
output grant_valid;
|
||||
input [3:0] request;
|
||||
input rst;
|
||||
endmodule
|
||||
|
||||
(* abc_box_id=1 *)
|
||||
module MUXF8(input I0, I1, S, output O);
|
||||
endmodule
|
||||
|
||||
// Citation: https://github.com/alexforencich/verilog-ethernet
|
||||
// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test022" abc9.v -q
|
||||
// returns before b4321a31
|
||||
// Warning: Wire abc9_test022.\m_eth_payload_axis_tkeep [7] is used but has no
|
||||
// driver.
|
||||
// Warning: Wire abc9_test022.\m_eth_payload_axis_tkeep [3] is used but has no
|
||||
// driver.
|
||||
module abc9_test022
|
||||
(
|
||||
input wire clk,
|
||||
input wire i,
|
||||
output wire [7:0] m_eth_payload_axis_tkeep
|
||||
);
|
||||
reg [7:0] m_eth_payload_axis_tkeep_reg = 8'd0;
|
||||
assign m_eth_payload_axis_tkeep = m_eth_payload_axis_tkeep_reg;
|
||||
always @(posedge clk)
|
||||
m_eth_payload_axis_tkeep_reg <= i ? 8'hff : 8'h0f;
|
||||
endmodule
|
||||
|
||||
// Citation: https://github.com/riscv/riscv-bitmanip
|
||||
// TODO: yosys -p "synth_xilinx -abc9 -top abc9_test023" abc9.v -q
|
||||
// returns before 14233843
|
||||
// Warning: Wire abc9_test023.\dout [1] is used but has no driver.
|
||||
module abc9_test023 #(
|
||||
parameter integer N = 2,
|
||||
parameter integer M = 2
|
||||
) (
|
||||
input [7:0] din,
|
||||
output [M-1:0] dout
|
||||
);
|
||||
wire [2*M-1:0] mask = {M{1'b1}};
|
||||
assign dout = (mask << din[N-1:0]) >> M;
|
||||
endmodule
|
||||
|
||||
module abc9_test024(input [3:0] i, output [3:0] o);
|
||||
abc9_test024_sub a(i[1:0], o[1:0]);
|
||||
endmodule
|
||||
|
||||
module abc9_test024_sub(input [1:0] i, output [1:0] o);
|
||||
assign o = i;
|
||||
endmodule
|
||||
|
||||
module abc9_test025(input [3:0] i, output [3:0] o);
|
||||
abc9_test024_sub a(i[2:1], o[2:1]);
|
||||
endmodule
|
||||
|
||||
module abc9_test026(output [3:0] o, p);
|
||||
assign o = { 1'b1, 1'bx };
|
||||
assign p = { 1'b1, 1'bx, 1'b0 };
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
#!/bin/bash
|
||||
|
||||
OPTIND=1
|
||||
seed="" # default to no seed specified
|
||||
while getopts "S:" opt
|
||||
do
|
||||
case "$opt" in
|
||||
S) arg="${OPTARG#"${OPTARG%%[![:space:]]*}"}" # remove leading space
|
||||
seed="SEED=$arg" ;;
|
||||
esac
|
||||
done
|
||||
shift "$((OPTIND-1))"
|
||||
|
||||
# check for Icarus Verilog
|
||||
if ! which iverilog > /dev/null ; then
|
||||
echo "$0: Error: Icarus Verilog 'iverilog' not found."
|
||||
exit 1
|
||||
fi
|
||||
|
||||
cp ../simple/*.v .
|
||||
DOLLAR='?'
|
||||
exec ${MAKE:-make} -f ../tools/autotest.mk $seed *.v EXTRA_FLAGS="-p 'hierarchy; synth -run coarse; opt -full; techmap; abc9 -lut 4 -box ../abc.box; stat; check -assert; select -assert-none t:${DOLLAR}_NOT_ t:${DOLLAR}_AND_ %%'"
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
module abc9_test027(output reg o);
|
||||
initial o = 1'b0;
|
||||
always @*
|
||||
o <= ~o;
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
read_verilog abc9.v
|
||||
proc
|
||||
design -save gold
|
||||
|
||||
abc9 -lut 4
|
||||
check
|
||||
design -stash gate
|
||||
|
||||
design -import gold -as gold
|
||||
design -import gate -as gate
|
||||
|
||||
miter -equiv -flatten -make_assert -make_outputs gold gate miter
|
||||
sat -verify -prove-asserts -show-ports miter
|
||||
|
||||
Loading…
Reference in New Issue