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Added freduce -stop

This commit is contained in:
Clifford Wolf 2014-03-06 18:14:26 +01:00
parent 4d07f88258
commit da5859a674
1 changed files with 18 additions and 3 deletions
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21
passes/sat/freduce.cc
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@ -31,7 +31,7 @@
namespace { namespace {
bool inv_mode; bool inv_mode;
int verbose_level; int verbose_level, reduce_counter, reduce_stop_at;
typedef std::map<RTLIL::SigBit, std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>>> drivers_t; typedef std::map<RTLIL::SigBit, std::pair<RTLIL::Cell*, std::set<RTLIL::SigBit>>> drivers_t;
struct equiv_bit_t struct equiv_bit_t
@ -648,7 +648,7 @@ struct FreduceWorker
int rewired_sigbits = 0; int rewired_sigbits = 0;
for (auto &grp : equiv) for (auto &grp : equiv)
{ {
log(" Using as master for group: %s\n", log_signal(grp.front().bit)); log(" [%d] Using as master for group: %s\n", ++reduce_counter, log_signal(grp.front().bit));
RTLIL::SigSpec inv_sig; RTLIL::SigSpec inv_sig;
for (size_t i = 1; i < grp.size(); i++) for (size_t i = 1; i < grp.size(); i++)
@ -692,6 +692,11 @@ struct FreduceWorker
rewired_sigbits++; rewired_sigbits++;
} }
if (reduce_counter == reduce_stop_at) {
log(" Reached limit passed using -stop option. Skipping all further reductions.\n");
break;
}
} }
log(" Rewired a total of %d signal bits in module %s.\n", rewired_sigbits, RTLIL::id2cstr(module->name)); log(" Rewired a total of %d signal bits in module %s.\n", rewired_sigbits, RTLIL::id2cstr(module->name));
@ -711,7 +716,7 @@ struct FreducePass : public Pass {
log("\n"); log("\n");
log("This pass performs functional reduction in the circuit. I.e. if two nodes are\n"); log("This pass performs functional reduction in the circuit. I.e. if two nodes are\n");
log("equivialent, they are merged to one node and one of the redundant drivers is\n"); log("equivialent, they are merged to one node and one of the redundant drivers is\n");
log("unconnected. A subsequent call to 'clean' will remove the redundant drivers.\n"); log("disconnected. A subsequent call to 'clean' will remove the redundant drivers.\n");
log("\n"); log("\n");
log(" -v, -vv\n"); log(" -v, -vv\n");
log(" enable verbose or very verbose output\n"); log(" enable verbose or very verbose output\n");
@ -719,6 +724,10 @@ struct FreducePass : public Pass {
log(" -inv\n"); log(" -inv\n");
log(" enable explicit handling of inverted signals\n"); log(" enable explicit handling of inverted signals\n");
log("\n"); log("\n");
log(" -stop <n>\n");
log(" stop after <n> reduction operations. this is mostly used for\n");
log(" debugging the freduce command itself.\n");
log("\n");
log("This pass is undef-aware, i.e. it considers don't-care values for detecting\n"); log("This pass is undef-aware, i.e. it considers don't-care values for detecting\n");
log("equivialent nodes.\n"); log("equivialent nodes.\n");
log("\n"); log("\n");
@ -728,6 +737,8 @@ struct FreducePass : public Pass {
} }
virtual void execute(std::vector<std::string> args, RTLIL::Design *design) virtual void execute(std::vector<std::string> args, RTLIL::Design *design)
{ {
reduce_counter = 0;
reduce_stop_at = 0;
verbose_level = 0; verbose_level = 0;
inv_mode = false; inv_mode = false;
@ -747,6 +758,10 @@ struct FreducePass : public Pass {
inv_mode = true; inv_mode = true;
continue; continue;
} }
if (args[argidx] == "-stop" && argidx+1 < args.size()) {
reduce_stop_at = atoi(args[++argidx].c_str());
continue;
}
break; break;
} }
extra_args(args, argidx, design); extra_args(args, argidx, design);