mirror of https://github.com/YosysHQ/yosys.git
Improvements in SF2 flow and demo
Signed-off-by: Clifford Wolf <clifford@clifford.at>
This commit is contained in:
parent
d03780c3f4
commit
da5181a3df
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@ -1,3 +1,4 @@
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/netlist.edn
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/netlist.edn
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/netlist.vm
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/netlist.vm
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/example.stp
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/proj
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/proj
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@ -1,6 +1,6 @@
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#!/bin/bash
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#!/bin/bash
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set -ex
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set -ex
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yosys -p 'synth_sf2 -top example -edif netlist.edn -vlog netlist.vm' example.v
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yosys -p 'synth_sf2 -noclkbuf -top example -edif netlist.edn -vlog netlist.vm' example.v
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export LM_LICENSE_FILE=${LM_LICENSE_FILE:-1702@localhost}
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export LM_LICENSE_FILE=${LM_LICENSE_FILE:-1702@localhost}
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/opt/microsemi/Libero_SoC_v12.0/Libero/bin/libero SCRIPT:libero.tcl
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/opt/microsemi/Libero_SoC_v12.0/Libero/bin/libero SCRIPT:libero.tcl
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cp proj/designer/example/export/example.stp .
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cp proj/designer/example/export/example.stp .
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@ -33,18 +33,23 @@ struct Sf2IobsPass : public Pass {
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log("\n");
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log("\n");
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log("Add SF2 I/O buffers to top module IOs as needed.\n");
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log("Add SF2 I/O buffers to top module IOs as needed.\n");
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log("\n");
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log("\n");
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log(" -noclkbuf\n");
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log(" Do not insert clock buffers\n");
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log("\n");
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}
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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{
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{
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bool noclkbuf_mode = false;
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log_header(design, "Executing sf2_iobs pass (insert IO buffers).\n");
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log_header(design, "Executing sf2_iobs pass (insert IO buffers).\n");
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size_t argidx;
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size_t argidx;
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for (argidx = 1; argidx < args.size(); argidx++)
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for (argidx = 1; argidx < args.size(); argidx++)
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{
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{
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// if (args[argidx] == "-singleton") {
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if (args[argidx] == "-noclkbuf") {
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// singleton_mode = true;
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noclkbuf_mode = true;
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// continue;
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continue;
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// }
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}
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break;
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break;
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}
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}
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extra_args(args, argidx, design);
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extra_args(args, argidx, design);
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@ -94,7 +99,7 @@ struct Sf2IobsPass : public Pass {
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if (wire->port_output) {
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if (wire->port_output) {
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buf_type = "\\OUTBUF";
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buf_type = "\\OUTBUF";
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buf_port = "\\D";
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buf_port = "\\D";
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} else if (clk_bits.count(canonical_bit)) {
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} else if (clk_bits.count(canonical_bit) && !noclkbuf_mode) {
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buf_type = "\\CLKBUF";
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buf_type = "\\CLKBUF";
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buf_port = "\\Y";
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buf_port = "\\Y";
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} else {
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} else {
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@ -63,6 +63,9 @@ struct SynthSf2Pass : public ScriptPass
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log(" -noiobs\n");
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log(" -noiobs\n");
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log(" run synthesis in \"block mode\", i.e. do not insert IO buffers\n");
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log(" run synthesis in \"block mode\", i.e. do not insert IO buffers\n");
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log("\n");
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log("\n");
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log(" -noclkbuf\n");
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log(" do not inser clock buffers, only simpe IO buffers\n");
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log("\n");
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log(" -retime\n");
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log(" -retime\n");
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log(" run 'abc' with -dff option\n");
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log(" run 'abc' with -dff option\n");
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log("\n");
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log("\n");
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@ -73,7 +76,7 @@ struct SynthSf2Pass : public ScriptPass
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}
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}
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string top_opt, edif_file, vlog_file, json_file;
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string top_opt, edif_file, vlog_file, json_file;
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bool flatten, retime, iobs;
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bool flatten, retime, iobs, clkbuf;
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void clear_flags() YS_OVERRIDE
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void clear_flags() YS_OVERRIDE
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{
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{
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@ -84,6 +87,7 @@ struct SynthSf2Pass : public ScriptPass
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flatten = true;
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flatten = true;
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retime = false;
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retime = false;
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iobs = true;
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iobs = true;
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clkbuf = true;
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}
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}
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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void execute(std::vector<std::string> args, RTLIL::Design *design) YS_OVERRIDE
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@ -130,6 +134,10 @@ struct SynthSf2Pass : public ScriptPass
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iobs = false;
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iobs = false;
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continue;
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continue;
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}
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}
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if (args[argidx] == "-noclkbuf") {
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clkbuf = false;
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continue;
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}
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break;
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break;
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}
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}
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extra_args(args, argidx, design);
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extra_args(args, argidx, design);
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@ -201,8 +209,10 @@ struct SynthSf2Pass : public ScriptPass
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if (check_label("map_iobs"))
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if (check_label("map_iobs"))
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{
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{
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if (iobs || help_mode)
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if (help_mode)
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run("sf2_iobs", "(unless -noiobs)");
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run("sf2_iobs [-noclkbuf]", "(unless -noiobs)");
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else if (iobs)
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run(clkbuf ? "sf2_iobs" : "sf2_iobs -noclkbuf");
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run("clean");
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run("clean");
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}
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}
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