riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

For now, short $_DFF_[NP]_ from ff_map.v at re-integration

This commit is contained in:
Eddie Hung 2019-06-15 09:08:18 -07:00
parent 2ef2aa997c
commit da487c4f31
1 changed files with 8 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
passes/techmap/abc9.cc
View File

@ -511,6 +511,7 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
// Remove all AND, NOT, and ABC box instances
// in preparation for stitching mapped_mod in
// Short $_DFF_[NP]_ cells used by ABC (FIXME)
dict<IdString, decltype(RTLIL::Cell::parameters)> erased_boxes;
for (auto it = module->cells_.begin(); it != module->cells_.end(); ) {
RTLIL::Cell* cell = it->second;
@ -518,6 +519,13 @@ void abc9_module(RTLIL::Design *design, RTLIL::Module *current_module, std::stri
it = module->cells_.erase(it);
continue;
}
else if (cell->type.in("$_DFF_N_", "$_DFF_P_")) {
SigBit D = cell->getPort("\\D");
SigBit Q = cell->getPort("\\Q");
module->connect(Q, D);
it = module->cells_.erase(it);
continue;
}
RTLIL::Module* box_module = design->module(cell->type);
if (box_module && box_module->attributes.count("\\abc_box_id")) {
erased_boxes.insert(std::make_pair(it->first, std::move(cell->parameters)));