mirror of https://github.com/YosysHQ/yosys.git
Add plib flag to specify custom primitive library path
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@ -47,6 +47,9 @@ struct SynthPass : public ScriptPass
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log(" -lut <k>\n");
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log(" -lut <k>\n");
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log(" perform synthesis for a k-LUT architecture (default 4).\n");
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log(" perform synthesis for a k-LUT architecture (default 4).\n");
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log("\n");
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log("\n");
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log(" -plib <primitive_library.v>\n");
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log(" use the specified Verilog file as a primitive library.\n");
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log("\n");
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log(" -run <from_label>[:<to_label>]\n");
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log(" -run <from_label>[:<to_label>]\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" only run the commands between the labels (see below). an empty\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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log(" from label is synonymous to 'begin', and empty to label is\n");
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@ -58,13 +61,14 @@ struct SynthPass : public ScriptPass
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log("\n");
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log("\n");
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}
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}
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string top_module;
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string top_module, plib;
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bool autotop, forvpr;
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bool autotop, forvpr;
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int lut;
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int lut;
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void clear_flags() override
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void clear_flags() override
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{
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{
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top_module.clear();
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top_module.clear();
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plib.clear();
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autotop = false;
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autotop = false;
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lut = 4;
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lut = 4;
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forvpr = false;
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forvpr = false;
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@ -106,6 +110,10 @@ struct SynthPass : public ScriptPass
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lut = atoi(args[++argidx].c_str());
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lut = atoi(args[++argidx].c_str());
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continue;
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continue;
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}
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}
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if (args[argidx] == "-plib" && argidx+1 < args.size()) {
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plib = args[++argidx];
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continue;
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}
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break;
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break;
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}
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}
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extra_args(args, argidx, design);
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extra_args(args, argidx, design);
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@ -131,6 +139,10 @@ struct SynthPass : public ScriptPass
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} else
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} else
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run(stringf("hierarchy -check -top %s", top_module.c_str()));
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run(stringf("hierarchy -check -top %s", top_module.c_str()));
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if (plib.empty())
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run("read_verilog -lib +/fabulous/prims.v");
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else
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run("read_verilog -lib " + plib);
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run("proc");
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run("proc");
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run("tribuf -logic");
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run("tribuf -logic");
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run("deminout");
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run("deminout");
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@ -144,7 +156,7 @@ struct SynthPass : public ScriptPass
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run("abc -lut $LUT_K -dress");
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run("abc -lut $LUT_K -dress");
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run("clean");
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run("clean");
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if (forvpr)
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if (forvpr)
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run("yosys techmap -D LUT_K=$LUT_K -map +/fabulous/cells_map.v");
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run("techmap -D LUT_K=$LUT_K -map +/fabulous/cells_map.v");
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run("clean");
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run("clean");
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run("hierarchy -check");
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run("hierarchy -check");
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run("stat");
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run("stat");
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