riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Get rid of output_port lookup

This commit is contained in:
Eddie Hung 2019-10-07 11:49:06 -07:00
parent 3879ca1398
commit d9fba95177
1 changed files with 8 additions and 14 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
backends/aiger/xaiger.cc
View File

@ -768,15 +768,14 @@ struct XAigerWriter
box_outputs += GetSize(w); box_outputs += GetSize(w);
for (int i = 0; i < GetSize(w); i++) { for (int i = 0; i < GetSize(w); i++) {
if (GetSize(w) == 1) if (GetSize(w) == 1)
holes_wire = holes_module->addWire(stringf("%s.%s", cell->name.c_str(), w->name.c_str())); holes_wire = holes_module->addWire(stringf("$abc%s.%s", cell->name.c_str(), log_id(w->name)));
else else
holes_wire = holes_module->addWire(stringf("%s.%s[%d]", cell->name.c_str(), w->name.c_str(), i)); holes_wire = holes_module->addWire(stringf("$abc%s.%s[%d]", cell->name.c_str(), log_id(w->name), i));
holes_wire->port_output = true; holes_wire->port_output = true;
holes_wire->port_id = port_id++; holes_wire->port_id = port_id++;
holes_module->ports.push_back(holes_wire->name); holes_module->ports.push_back(holes_wire->name);
if (holes_cell) { if (holes_cell)
port_sig.append(holes_wire); port_sig.append(holes_wire);
}
else else
holes_module->connect(holes_wire, State::S0); holes_module->connect(holes_wire, State::S0);
} }
@ -862,15 +861,6 @@ struct XAigerWriter
// instead of per write_xaiger call // instead of per write_xaiger call
Pass::call_on_module(holes_module->design, holes_module, "flatten -wb; techmap; aigmap"); Pass::call_on_module(holes_module->design, holes_module, "flatten -wb; techmap; aigmap");
dict<SigBit, Wire*> output_port;
SigMap holes_sigmap(holes_module);
for (auto port_name : holes_module->ports) {
Wire *port = holes_module->wire(port_name);
if (port->port_input)
continue;
output_port.insert(std::make_pair(holes_sigmap(port), port));
}
dict<SigSig, SigSig> replace; dict<SigSig, SigSig> replace;
for (auto it = holes_module->cells_.begin(); it != holes_module->cells_.end(); ) { for (auto it = holes_module->cells_.begin(); it != holes_module->cells_.end(); ) {
auto cell = it->second; auto cell = it->second;
@ -879,7 +869,11 @@ struct XAigerWriter
SigBit Q = cell->getPort("\\Q"); SigBit Q = cell->getPort("\\Q");
// Remove the DFF cell from what needs to be a combinatorial box // Remove the DFF cell from what needs to be a combinatorial box
it = holes_module->cells_.erase(it); it = holes_module->cells_.erase(it);
Wire *port = output_port.at(Q); Wire *port;
if (GetSize(Q.wire) == 1)
port = holes_module->wire(stringf("$abc%s", Q.wire->name.c_str()));
else
port = holes_module->wire(stringf("$abc%s[%d]", Q.wire->name.c_str(), Q.offset));
log_assert(port); log_assert(port);
// Prepare to replace "assign <port> = DFF.Q;" with "assign <port> = DFF.D;" // Prepare to replace "assign <port> = DFF.Q;" with "assign <port> = DFF.D;"
// in order to extract the combinatorial control logic that feeds the box // in order to extract the combinatorial control logic that feeds the box