riscv
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Projects Releases Wiki Activity

Merge pull request #1377 from YosysHQ/clifford/fixzdigit 

Fix handling of z_digit "?" and fix optimization of cmp with "z"
This commit is contained in:
Clifford Wolf 2019-09-15 11:04:31 +02:00 committed by GitHub
parent 4da6e19fe1 a67d63714b
commit d9f99745da
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
2 changed files with 5 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
frontends/verilog/const2ast.cc
View File

@ -85,10 +85,8 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
digits.push_back(10 + *str - 'A'); digits.push_back(10 + *str - 'A');
else if (*str == 'x' || *str == 'X') else if (*str == 'x' || *str == 'X')
digits.push_back(0xf0); digits.push_back(0xf0);
else if (*str == 'z' || *str == 'Z') else if (*str == 'z' || *str == 'Z' || *str == '?')
digits.push_back(0xf1); digits.push_back(0xf1);
else if (*str == '?')
digits.push_back(0xf2);
str++; str++;
} }
@ -112,8 +110,6 @@ static void my_strtobin(std::vector<RTLIL::State> &data, const char *str, int le
data.push_back(case_type == 'x' ? RTLIL::Sa : RTLIL::Sx); data.push_back(case_type == 'x' ? RTLIL::Sa : RTLIL::Sx);
else if (*it == 0xf1) else if (*it == 0xf1)
data.push_back(case_type == 'x' || case_type == 'z' ? RTLIL::Sa : RTLIL::Sz); data.push_back(case_type == 'x' || case_type == 'z' ? RTLIL::Sa : RTLIL::Sz);
else if (*it == 0xf2)
data.push_back(RTLIL::Sa);
else else
data.push_back((*it & bitmask) ? State::S1 : State::S0); data.push_back((*it & bitmask) ? State::S1 : State::S0);
} }

4
passes/opt/opt_expr.cc
View File

@ -953,6 +953,10 @@ void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bool cons
} }
if (b.is_fully_const()) { if (b.is_fully_const()) {
if (b.is_fully_undef()) {
RTLIL::SigSpec input = b;
ACTION_DO(ID::Y, Const(State::Sx, GetSize(cell->getPort(ID::Y))));
} else
if (b.as_bool() == (cell->type == ID($eq))) { if (b.as_bool() == (cell->type == ID($eq))) {
RTLIL::SigSpec input = b; RTLIL::SigSpec input = b;
ACTION_DO(ID::Y, cell->getPort(ID::A)); ACTION_DO(ID::Y, cell->getPort(ID::A));